MerryMage
bfd65bedfe
A64: Implement DSB, DMB
2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d
Implement DC instructions
2020-04-22 20:46:14 +01:00
Lioncash
a9153218bd
A64: Implement NOT (vector)
2020-04-22 20:46:14 +01:00
MerryMage
2cb0a699ba
IR: Implement FPMax, FPMin
2020-04-22 20:46:14 +01:00
MerryMage
aed4fd3ec3
A64: Implement FADD (vector), vector variant
2020-04-22 20:46:14 +01:00
MerryMage
98c8e7d1af
IR: Implement FPVectorAdd
2020-04-22 20:46:14 +01:00
MerryMage
5f77ab28ee
A64: Implement SSHLL, SSHLL2
2020-04-22 20:46:14 +01:00
MerryMage
eae518a338
IR: Implement VectorSignExtend
2020-04-22 20:46:14 +01:00
MerryMage
3738043e58
A64: Implement DUP (element), vector variant
2020-04-22 20:46:14 +01:00
MerryMage
ce7628b6b5
load_store_multiple_structures: Improve IR codegen for selem == 1 case
2020-04-22 20:46:14 +01:00
MerryMage
f1cb5581c9
A64: Implement FSUB (vector)
2020-04-22 20:46:14 +01:00
MerryMage
b9cd345ddc
IR: Implement FPVectorSub
2020-04-22 20:46:14 +01:00
MerryMage
f378d2ef1b
Forward declare IR::Opcode and IR::Type where possible
2020-04-22 20:46:14 +01:00
MerryMage
6c9b4f0114
A64: Implement CNT
2020-04-22 20:46:14 +01:00
MerryMage
303088a51e
IR: Implement VectorPopulationCount
2020-04-22 20:46:14 +01:00
MerryMage
1dd2b33b87
A64: Implement MLS (vector)
2020-04-22 20:46:14 +01:00
MerryMage
5eac3abf52
A64: Implement MLA (vector)
2020-04-22 20:46:14 +01:00
MerryMage
3afd2fcbad
A64: Implement MUL (vector)
2020-04-22 20:46:14 +01:00
MerryMage
b6de612e01
IR: Implement VectorMultiply
2020-04-22 20:46:14 +01:00
MerryMage
e7041d7196
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
2020-04-22 20:46:14 +01:00
MerryMage
a455ff70c9
decoder/a64: Don't rearrange unrelated decoders
2020-04-22 20:46:14 +01:00
MerryMage
faeb77e8c4
A64: Implement SUB (vector)
2020-04-22 20:46:14 +01:00
MerryMage
bd106c3ae7
A64: Implement SIMD instruction SSRA, vector variant
2020-04-22 20:46:14 +01:00
MerryMage
f58aba9871
A64: Implement SIMD instruction SSHR, vector variant
2020-04-22 20:46:14 +01:00
MerryMage
715ae1c229
IR: Implement VectorArithmeticShiftRight
2020-04-22 20:46:14 +01:00
MerryMage
653c82d8f0
impl: Improve Vpart setter
2020-04-22 20:46:14 +01:00
MerryMage
e858ce0b35
A64: Implement SIMD instructions XTN, XTN2
2020-04-22 20:46:13 +01:00
MerryMage
132c783320
IR: Implement VectorNarrow
2020-04-22 20:46:13 +01:00
MerryMage
cbc9f361b0
IR: Implement VectorSub
2020-04-22 20:46:13 +01:00
MerryMage
3f93c77ace
A64: Implement SIMD instruction USRA, vector variant
2020-04-22 20:46:13 +01:00
MerryMage
fb9d20f27f
A64: Implement SIMD instruction USHR, vector variant
2020-04-22 20:46:13 +01:00
MerryMage
b22c5961f9
IR: Implement VectorLogicalShiftRight
2020-04-22 20:46:13 +01:00
MerryMage
7ff280827b
A64: Implement SIMD instructions USHLL, USHLL2
2020-04-22 20:46:13 +01:00
MerryMage
59ace60b03
IR: Implement VectorZeroExtend
2020-04-22 20:46:13 +01:00
MerryMage
d3a4e1efe2
IR: Vector instructions now take esize argument in emitter
2020-04-22 20:46:13 +01:00
MerryMage
1d0cd95b23
A64: Implement SIMD instruction SHL
2020-04-22 20:46:13 +01:00
MerryMage
f6247125c0
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2020-04-22 20:46:13 +01:00
MerryMage
15e8231f24
opcodes: Sort vector IR opcodes alphabetically
2020-04-22 20:46:13 +01:00
FernandoS27
15871910af
Implemented BSL, BIC, BIT and BIF vector instructions
2020-04-22 20:46:13 +01:00
MerryMage
ba4a779c62
A32/decoder/arm: bug: Correct bitstring for SRS
2020-04-22 20:46:13 +01:00
Lioncash
4e33629b0e
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
2020-04-22 20:46:13 +01:00
Lioncash
35a29a9665
A64: Implement ZIP1
2020-04-22 20:46:13 +01:00
FernandoS27
586854117b
Implemented UMULH and SMULH instructions
2020-04-22 20:46:13 +01:00
MerryMage
1a7b7b541a
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
...
There wasn't a clean way to seperate these instructions out.
2020-04-22 20:46:13 +01:00
MerryMage
8ab7d8175c
impl: Add AdvSIMDExpandImm
2020-04-22 20:46:13 +01:00
MerryMage
ea69cb4474
A64: Implement SUB (vector), scalar variant
2020-04-22 20:46:13 +01:00
MerryMage
4c5871d5d5
A64: Implement ADD (vector), scalar variant
2020-04-22 20:46:13 +01:00
MerryMage
2a0850c068
A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
2020-04-22 20:46:13 +01:00
MerryMage
7b33772ac6
A64: Implement BIC (vector, register)
2020-04-22 20:46:13 +01:00
MerryMage
eb5591859c
A64: Implement FMOV (general)
2020-04-22 20:46:13 +01:00
MerryMage
dd88cee15a
translate/impl: Add Vpart
2020-04-22 20:46:13 +01:00
MerryMage
cc9efd13c9
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
2020-04-22 20:46:13 +01:00
MerryMage
81713c2b77
A64: Implement FCCMPE
2020-04-22 20:46:13 +01:00
MerryMage
ef906dbbfa
A64: Implement FCCMP
2020-04-22 20:46:13 +01:00
MerryMage
aac5af50e2
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2020-04-22 20:46:13 +01:00
Lioncash
2ee39d6b36
A64: Implement FMOV (register)
2020-04-22 20:46:13 +01:00
MerryMage
b02b861242
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
2020-04-22 20:46:13 +01:00
Lioncash
5a65313236
A64: Implement CCMP (immediate)
2020-04-22 20:46:13 +01:00
Lioncash
ab4664de61
A64: Implement CCMN (immediate)
2020-04-22 20:46:13 +01:00
Lioncash
a6c6539109
A64: Implement CCMP (register)
2020-04-22 20:46:13 +01:00
Lioncash
22632db337
microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
2020-04-22 20:46:13 +01:00
MerryMage
c5033b5dda
A64: Implement CCMN (register)
2020-04-22 20:46:13 +01:00
MerryMage
dd2a6684fe
IR: Add ConditionalSelectNZCV instruction
2020-04-22 20:46:13 +01:00
MerryMage
4491746eae
A64: Implement FNEG
2020-04-22 20:46:13 +01:00
MerryMage
db958061a3
A64: Implement FABS
2020-04-22 20:46:13 +01:00
MerryMage
8765b421b7
A64: Implement FCSEL
2020-04-22 20:46:13 +01:00
MerryMage
7e82d8eede
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
2020-04-22 20:46:13 +01:00
MerryMage
2409e5d082
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
2020-04-22 20:46:13 +01:00
MerryMage
56bc7825ef
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
2020-04-22 20:46:13 +01:00
Lioncash
40614202e7
A64: Implement AESD
2020-04-22 20:46:13 +01:00
Lioncash
ccef85dbb7
A64: Implement AESE
2020-04-22 20:46:13 +01:00
MerryMage
8931ee346b
IR: Add IR instruction NZCVFromPackedFlags
...
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2020-04-22 20:46:13 +01:00
MerryMage
0bb4474fb9
A64: Implement INS (general)
2020-04-22 20:46:13 +01:00
MerryMage
d13704fdef
A64: Implement INS (element)
2020-04-22 20:46:13 +01:00
MerryMage
0642d49919
A64: Implement SMOV
2020-04-22 20:46:13 +01:00
MerryMage
5297027ebe
A64: Implement UMOV
2020-04-22 20:46:13 +01:00
MerryMage
47661b746b
basic_block: Fix bogus GCC maybe-uninitialized warning
2020-04-22 20:46:13 +01:00
MerryMage
1fb0957aa3
A64: Implement FCVT
2020-04-22 20:46:13 +01:00
MerryMage
ca38225e08
fuzz_with_unicorn: Skip instructions that need to be interpreted
2020-04-22 20:46:13 +01:00
MerryMage
4be55b8b84
A64: Implement FMOV (scalar, immediate)
2020-04-22 20:46:13 +01:00
MerryMage
a07c05ea51
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
2020-04-22 20:46:13 +01:00
MerryMage
93fcbdf1e2
A64: Implement FCMP, FCMPE
2020-04-22 20:46:13 +01:00
MerryMage
99d8ebe4d5
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
2020-04-22 20:46:13 +01:00
MerryMage
429dc24587
IR: Merge U32 and U64 variants of FP instructions
2020-04-22 20:46:13 +01:00
MerryMage
ed2bedec43
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2020-04-22 20:46:13 +01:00
MerryMage
ebfc51c609
IR: Implement VectorSetElement{8,16,32,64}
2020-04-22 20:46:13 +01:00
Lioncash
a5c4fbc783
A64: Implement AESIMC and AESMC
2020-04-22 20:46:13 +01:00
Lioncash
af1384d700
A64: Implement CRC32
2020-04-22 20:46:12 +01:00
MerryMage
cc0eb18a0b
A32: data_processing: Remove !S assertions
2020-04-22 20:46:12 +01:00
MerryMage
865a30eb0d
A32: Implement BKPT
2020-04-22 20:46:12 +01:00
MerryMage
f023bbb893
A32: Add ExceptionRaised IR instruction and use it
2020-04-22 20:46:12 +01:00
Lioncash
7ffbebf290
A64: Implement CRC32C
2020-04-22 20:46:12 +01:00
MerryMage
d7044bc751
assert: Use fmt in ASSERT_MSG
2020-04-22 20:46:12 +01:00
MerryMage
52268298a8
a64_emit_x64: Perform RSB predictions
2020-04-22 20:46:12 +01:00
MerryMage
98ec9c5f90
A32: Change UserCallbacks to be similar to A64's interface
2020-04-22 20:46:12 +01:00
MerryMage
6fc228f7fd
ir_opt: Add A64 Get/Set Elimination Pass
2020-04-22 20:46:12 +01:00
MerryMage
e01b500aea
ir_emitter: Allow the insertion point for new instructions to be set
2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050
A64: Implement EXTR
2020-04-22 20:46:12 +01:00
MerryMage
88ae7fce52
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
2020-04-22 20:44:38 +01:00
MerryMage
b513b2ef05
IR: Implement IR instructions A64{Get,Set}S
2020-04-22 20:44:38 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
...
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
Lioncash
7abd673a49
A64: Zero upper 64 bits in ORN if using the 64-bit variant
...
Resolves a TODO
2020-04-22 20:44:38 +01:00
MerryMage
ba3d6da0c8
load_store_register_unprivileged: bug: LDTRSW
2020-04-22 20:44:38 +01:00
MerryMage
75756137c6
A64: Implement CMEQ (register, vector)
2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions ( #142 )
2020-04-22 20:44:38 +01:00
MerryMage
94383fd934
microinstruction: Missed A64{Read,Write}Memory128 from opcode information
2020-04-22 20:44:38 +01:00
James Rowe
589ad7232f
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
2020-04-22 20:44:38 +01:00
James Rowe
ae880d8391
A64: Fix bugs and address review comments
2020-04-22 20:44:38 +01:00
James Rowe
3aeb7ca50c
Add missing returns
2020-04-22 20:44:38 +01:00
James Rowe
41e6e659c5
A64: Implement Load/Store register (unprivileged)
2020-04-22 20:44:37 +01:00
MerryMage
285fd22c30
IR: Add IR instruction VectorZeroUpper
2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806
Implemented SDIV and UDIV instructions
2020-04-22 20:44:37 +01:00
MerryMage
6033b05ca6
A64: Implement LDR/STR (immediate, SIMD&FP)
2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621
IR: Add IR instructions A64Memory{Read,Write}128
...
This implementation only works on macOS and Linux.
2020-04-22 20:44:37 +01:00
MerryMage
e00a522cba
IR: Add IR instruction VectorGetElement{8,16,32,64}
2020-04-22 20:44:37 +01:00
MerryMage
28ccd85e5c
IR: Add IR instruction ZeroExtendToQuad
2020-04-22 20:44:37 +01:00
MerryMage
3caf192f60
A64: Implement DUP (general)
2020-04-22 20:44:37 +01:00
MerryMage
793753bf63
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
2020-04-22 20:44:37 +01:00
Lioncash
8ee854232c
General: Default constructors and destructors where applicable
2020-04-22 20:44:37 +01:00
Lioncash
d1e4526e1c
ir_emitter: Remove unused includes
2020-04-22 20:44:37 +01:00
Lioncash
6f9216d544
A64: Implement RBIT
2020-04-22 20:44:37 +01:00
MerryMage
9b0a21915f
ir_emitted: Remove unimplemented IR instruction Unimplemented
2020-04-22 20:44:37 +01:00
MerryMage
d4b05b28cf
A64: Implement CLS
...
This is not the cleanest implementation.
2020-04-22 20:42:46 +01:00
MerryMage
b8e26bfdc3
A64: Implement ADDP (vector)
2020-04-22 20:42:46 +01:00
MerryMage
eaf545877a
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
2020-04-22 20:42:46 +01:00
MerryMage
394bd57bb6
microinstruction: bug: Add missing opcodes
2020-04-22 20:42:46 +01:00
Lioncash
bb1c5bd3b2
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
2020-04-22 20:42:46 +01:00
Lioncash
c1a25bfc2f
A64: Implement MADD and MSUB
2020-04-22 20:42:46 +01:00
Lioncash
b7c5055d42
A64: Implement CLZ
2020-04-22 20:42:46 +01:00
Lioncash
b612782445
opcodes: Add 64-bit CountLeadingZeroes opcode
2020-04-22 20:42:46 +01:00
MerryMage
4c4efb2213
data_processing_register: Clean-up
2020-04-22 20:42:46 +01:00
Lioncash
ae5dbcbed6
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
...
Truly the most difficult A64 instructions to implement.
2020-04-22 20:42:46 +01:00
Lioncash
4d8f4aa8af
A64: Implement ASRV, LSLV, LSRV, and RORV
2020-04-22 20:42:46 +01:00
Lioncash
a8a65beb2b
data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG
2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536
A64: Implement AND (vector)
2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
Thomas Guillemard
896cf44f96
A64: Implement REV, REV32, and REV16 ( #126 )
2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc
reg_alloc: Consider bitwidth of data and registers when emitting instructions
2020-04-22 20:42:46 +01:00
MerryMage
144b629d8a
A64: Implement CSEL
2020-04-22 20:42:45 +01:00
MerryMage
6395f09f94
IR: Implement Conditional Select
2020-04-22 20:42:45 +01:00
MerryMage
19da68568e
A64/translate/branch: bug: Read-after-write error in BLR
2020-04-22 20:42:45 +01:00
MerryMage
9f57283a30
A64: Implement SBFM, BFM, UBFM
2020-04-22 20:42:45 +01:00
MerryMage
cdbc8d07a5
A64: Implement MOVN, MOVZ, MOVK
2020-04-22 20:42:45 +01:00
MerryMage
ecebe14a01
ir/location_descriptor: Add missing <functional> header for std::hash
2020-04-22 20:42:45 +01:00
MerryMage
c6a091d874
A64: Optimization: Merge interpret blocks
2020-04-22 20:42:45 +01:00
MerryMage
21fe61eac6
A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
2020-04-22 20:42:45 +01:00
MerryMage
7c4b70751c
A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
2020-04-22 20:42:45 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
61125d6dd1
A64/translate: Add TranslateSingleInstruction function
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
a1dfa01515
imm: Suppress MSVC warning C4244: value will never be truncated
2020-04-22 20:42:45 +01:00
MerryMage
26da149639
imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions
2020-04-22 20:42:45 +01:00
MerryMage
b34c6616d4
A64/decoder: Split decoder data from header
2020-04-22 20:42:45 +01:00
MerryMage
595f157e5e
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
511215342b
A64/location_descriptor: Fix -fpermissive warning on GCC
2020-04-22 20:42:45 +01:00
MerryMage
243f06c613
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
25411da838
A32: Implement load stores (immediate)
2020-04-22 20:42:45 +01:00
MerryMage
2aadeec291
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
9e27e4d250
imm: bug: SignExtend wasn't working for T with bit size > 32
2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48
A64: Implement compare and branch
2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5
A64: PSTATE access and tests
2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3
A64: Implement branch (register)
2020-04-22 20:42:45 +01:00
MerryMage
86d1095df7
A64: Implement branch
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
5a1d88c5dc
A64: Implement pcrel
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93
A64: Backend framework
2020-04-22 20:42:44 +01:00
MerryMage
e161cf16f5
A64: Initial framework
2020-04-22 20:42:44 +01:00
MerryMage
f61da0b5a9
IR: Compile-time type-checking of IR
2020-04-22 20:39:27 +01:00
MerryMage
44f7f04b5c
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2020-04-22 20:39:27 +01:00
MerryMage
83022322d1
Make IR->A32 LocationDescriptor conversion explicit
2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1
Final A32 refactor
2020-04-22 20:39:27 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
MerryMage
4393473d06
interface: Allow saving and storing of contexts
2020-04-22 20:26:40 +01:00
MerryMage
19a7fb8992
jit_state: Split off CPSR.NZCV
2020-04-22 20:26:40 +01:00
MerryMage
311361b409
jit_state: Split off CPSR.{E,T}
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This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72
emit_x64: Use boost::icl::interval_map to speed up ranged invalidation
2020-04-22 20:26:40 +01:00
MerryMage
80c56aa89d
Remove unnecessary use of boost::make_optional
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Closes #119 .
2020-04-22 20:26:12 +01:00
MerryMage
de6a93a160
decoder_detail: Lambda captures may be unused if iota is an empty sequence
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Closes #120
2020-04-22 20:26:12 +01:00
MerryMage
3141dadea9
Remove UNUSED macro
2020-04-22 20:26:12 +01:00
MerryMage
7cac9519b0
microinstruction: Remove DecrementRemainingUses
2020-04-22 20:26:12 +01:00
MerryMage
5d72f7048f
basic_block: Add inst address and use count to DumpBlock
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This additional output assists with debugging.
2020-04-22 20:26:12 +01:00
MerryMage
d1e0a29cd9
Implement IR instruction PackedSelect, reimplement SEL
2020-04-22 20:26:07 +01:00
MerryMage
814e378249
VCMP and VCMPE were the other way around
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- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
2020-04-22 20:26:07 +01:00
MerryMage
29471be317
Standardize location of storage-class specifiers: Place at beginning of declarations
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Justification: C99 specifies that doing otherwise is an obsolescent feature.
2017-09-29 01:23:45 +01:00
MerryMage
993e142c6b
disassembler: Fix RegList
2017-08-05 01:57:29 +01:00
MerryMage
6197bde0fc
disassembler_arm: Fix disassembly of LDRH (reg)
2017-07-30 18:45:55 +01:00
MerryMage
599a613fea
Move SEL from status_register_access to misc
2017-04-25 13:57:27 +01:00
MerryMage
50bb317104
parallel: UQADD8 and UQADD16 are unpredictable when {d|n|m} == 15
2017-04-25 13:45:31 +01:00
MerryMage
7639dfea51
coprocessor: Use && instead of & with boolean arguments
2017-04-22 15:05:31 +01:00
MerryMage
1c21ae6bcd
saturated: Implement QASX, QSAX, UQASX, UQSAX
2017-04-10 10:21:51 +01:00
MerryMage
523ae542f4
microinstruction: Implement HasAssociatedPseudoOperation
2017-04-04 13:10:50 +01:00
MerryMage
05e97058c3
parallel: Add and Subtract with Exchange improvements
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* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8
Ranged cache invalidation
2017-03-20 11:58:25 +00:00