MerryMage 1d0cd95b23 A64: Implement SIMD instruction SHL		2020-04-22 20:46:13 +01:00
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A32	A32/decoder/arm: bug: Correct bitstring for SRS	2020-04-22 20:46:13 +01:00
A64	A64: Implement SIMD instruction SHL	2020-04-22 20:46:13 +01:00
decoder	General: Convert multiple namespace specifiers to nested namespace specifiers where applicable	2020-04-22 20:44:38 +01:00
ir	IR: Implement VectorLogicalShiftLeft{8,16,32,64}	2020-04-22 20:46:13 +01:00