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A64: Implement ASRV, LSLV, LSRV, and RORV

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Lioncash 2018-01-21 22:28:24 -05:00 committed by MerryMage
parent a8a65beb2b
commit 4d8f4aa8af
3 changed files with 71 additions and 4 deletions
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1
src/CMakeLists.txt
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@ -66,6 +66,7 @@ add_library(dynarmic
frontend/A64/translate/impl/data_processing_logical.cpp
frontend/A64/translate/impl/data_processing_pcrel.cpp
frontend/A64/translate/impl/data_processing_register.cpp
frontend/A64/translate/impl/data_processing_shift.cpp
frontend/A64/translate/impl/exception_generating.cpp
frontend/A64/translate/impl/impl.cpp
frontend/A64/translate/impl/impl.h

8
src/frontend/A64/decoder/a64.inc
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@ -276,10 +276,10 @@ INST(UnallocatedEncoding, "", "10111
// Data Processing - Register - 2 source
//INST(UDIV, "UDIV", "z0011010110mmmmm000010nnnnnddddd")
//INST(SDIV, "SDIV", "z0011010110mmmmm000011nnnnnddddd")
//INST(LSLV, "LSLV", "z0011010110mmmmm001000nnnnnddddd")
//INST(LSRV, "LSRV", "z0011010110mmmmm001001nnnnnddddd")
//INST(ASRV, "ASRV", "z0011010110mmmmm001010nnnnnddddd")
//INST(RORV, "RORV", "z0011010110mmmmm001011nnnnnddddd")
INST(LSLV, "LSLV", "z0011010110mmmmm001000nnnnnddddd")
INST(LSRV, "LSRV", "z0011010110mmmmm001001nnnnnddddd")
INST(ASRV, "ASRV", "z0011010110mmmmm001010nnnnnddddd")
INST(RORV, "RORV", "z0011010110mmmmm001011nnnnnddddd")
//INST(CRC32, "CRC32B, CRC32H, CRC32W, CRC32X", "z0011010110mmmmm0100zznnnnnddddd")
//INST(CRC32C, "CRC32CB, CRC32CH, CRC32CW, CRC32CX", "z0011010110mmmmm0101zznnnnnddddd")
//INST(PACGA, "PACGA", "10011010110mmmmm001100nnnnnddddd")

66
src/frontend/A64/translate/impl/data_processing_shift.cpp Normal file
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@ -0,0 +1,66 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2018 MerryMage
* This software may be used and distributed according to the terms of the GNU
* General Public License version 2 or any later version.
*/
#include "frontend/A64/translate/impl/impl.h"
namespace Dynarmic {
namespace A64 {
static IR::U8 SanitizeShiftAmount(TranslatorVisitor& tv, IREmitter& ir, size_t datasize,
const IR::U32U64& amount) {
return ir.LeastSignificantByte(ir.And(amount, tv.I(datasize, datasize - 1)));
}
bool TranslatorVisitor::LSLV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 operand = X(datasize, Rn);
const IR::U32U64 shift_amount = X(datasize, Rm);
const IR::U32U64 result = ir.LogicalShiftLeft(operand, SanitizeShiftAmount(*this, ir, datasize, shift_amount));
X(datasize, Rd, result);
return true;
}
bool TranslatorVisitor::LSRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 operand = X(datasize, Rn);
const IR::U32U64 shift_amount = X(datasize, Rm);
const IR::U32U64 result = ir.LogicalShiftRight(operand, SanitizeShiftAmount(*this, ir, datasize, shift_amount));
X(datasize, Rd, result);
return true;
}
bool TranslatorVisitor::ASRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 operand = X(datasize, Rn);
const IR::U32U64 shift_amount = X(datasize, Rm);
const IR::U32U64 result = ir.ArithmeticShiftRight(operand, SanitizeShiftAmount(*this, ir, datasize, shift_amount));
X(datasize, Rd, result);
return true;
}
bool TranslatorVisitor::RORV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 operand = X(datasize, Rn);
const IR::U32U64 shift_amount = X(datasize, Rm);
const IR::U32U64 result = ir.RotateRight(operand, SanitizeShiftAmount(*this, ir, datasize, shift_amount));
X(datasize, Rd, result);
return true;
}
} // namespace A64
} // namespace Dynarmic