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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)

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MerryMage 2018-02-02 22:39:24 +00:00
parent 93fcbdf1e2
commit a07c05ea51
3 changed files with 24 additions and 4 deletions
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4
src/frontend/A64/decoder/a64.inc
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@ -180,8 +180,8 @@ INST(STURx_LDURx, "STURx/LDURx", "zz111
INST(UnallocatedEncoding, "", "111110001-0---------00----------")
INST(UnallocatedEncoding, "", "10111000110---------00----------")
//INST(PRFM_imm, "PRFM (immediate)", "1111100110iiiiiiiiiiiinnnnnttttt")
//INST(STUR_fpsimd, "STUR (SIMD&FP)", "zz111100-00iiiiiiiii00nnnnnttttt")
//INST(LDUR_fpsimd, "LDUR (SIMD&FP)", "zz111100-10iiiiiiiii00nnnnnttttt")
INST(STUR_fpsimd, "STUR (SIMD&FP)", "zz111100o00iiiiiiiii00nnnnnttttt")
INST(LDUR_fpsimd, "LDUR (SIMD&FP)", "zz111100o10iiiiiiiii00nnnnnttttt")
// Loads and stores - Load/Store register (immediate pre/post-indexed)
INST(STRx_LDRx_imm_1, "STRx/LDRx (immediate)", "zz111000oo0iiiiiiiiip1nnnnnttttt")

4
src/frontend/A64/translate/impl/impl.h
View file

@ -246,8 +246,8 @@ struct TranslatorVisitor final {
bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt);
bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt);
bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt);
bool STUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
bool LDUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt);
bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt);
// Loads and stores - Load/Store register (unprivileged)
bool STTRB(Imm<9> imm9, Reg Rn, Reg Rt);

20
src/frontend/A64/translate/impl/load_store_register_immediate.cpp
View file

@ -193,4 +193,24 @@ bool TranslatorVisitor::LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm1
return LoadStoreSIMD(*this, ir, wback, postindex, scale, offset, MemOp::LOAD, Rn, Vt);
}
bool TranslatorVisitor::STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
const bool wback = false;
const bool postindex = false;
const size_t scale = concatenate(opc_1, size).ZeroExtend<size_t>();
if (scale > 4) return UnallocatedEncoding();
const u64 offset = imm9.SignExtend<u64>();
return LoadStoreSIMD(*this, ir, wback, postindex, scale, offset, MemOp::STORE, Rn, Vt);
}
bool TranslatorVisitor::LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
const bool wback = false;
const bool postindex = false;
const size_t scale = concatenate(opc_1, size).ZeroExtend<size_t>();
if (scale > 4) return UnallocatedEncoding();
const u64 offset = imm9.SignExtend<u64>();
return LoadStoreSIMD(*this, ir, wback, postindex, scale, offset, MemOp::LOAD, Rn, Vt);
}
} // namespace Dynarmic::A64