A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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81713c2b77
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cc9efd13c9
3 changed files with 30 additions and 3 deletions
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@ -132,9 +132,9 @@ INST(LDx_mult_2, "LDx (multiple structures)", "0Q001
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//INST(LDAXRB, "LDAXRB", "zz00100001011111111111nnnnnttttt")
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//INST(LDXP, "LDXP", "1z001000011111110uuuuunnnnnttttt")
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//INST(LDAXP, "LDAXP", "1z001000011111111uuuuunnnnnttttt")
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//INST(STLLR, "STLLRB, STLLRH, STLLR", "zz00100010011111011111nnnnnttttt")
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INST(STLLR, "STLLRB, STLLRH, STLLR", "zz00100010011111011111nnnnnttttt")
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INST(STLR, "STLRB, STLRH, STLR", "zz00100010011111111111nnnnnttttt")
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//INST(LDLAR, "LDLARB, LDLARH, LDLAR", "zz00100011011111011111nnnnnttttt")
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INST(LDLAR, "LDLARB, LDLARH, LDLAR", "zz00100011011111011111nnnnnttttt")
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INST(LDAR, "LDARB, LDARH, LDAR", "zz00100011011111111111nnnnnttttt")
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//INST(CASP, "CASP, CASPA, CASPAL, CASPL", "0z0010000L1sssssp11111nnnnnttttt") // ARMv8.1
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//INST(CASB, "CASB, CASAB, CASALB, CASLB", "000010001L1sssssp11111nnnnnttttt") // ARMv8.1
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@ -47,6 +47,13 @@ static bool OrderedSharedDecodeAndOperation(TranslatorVisitor& tv, size_t size,
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return true;
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}
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bool TranslatorVisitor::STLLR(Imm<2> sz, Reg Rn, Reg Rt) {
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const size_t size = sz.ZeroExtend<size_t>();
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const bool L = 0;
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const bool o0 = 0;
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return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
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}
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bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) {
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const size_t size = sz.ZeroExtend<size_t>();
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const bool L = 0;
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@ -54,6 +61,13 @@ bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) {
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return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
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}
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bool TranslatorVisitor::LDLAR(Imm<2> sz, Reg Rn, Reg Rt) {
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const size_t size = sz.ZeroExtend<size_t>();
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const bool L = 1;
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const bool o0 = 0;
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return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
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}
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bool TranslatorVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) {
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const size_t size = sz.ZeroExtend<size_t>();
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const bool L = 1;
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@ -4,7 +4,10 @@
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include <cstring>
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#include <string>
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#include <vector>
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#include <catch.hpp>
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@ -41,8 +44,18 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) {
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std::vector<InstructionGenerator> result;
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// List of instructions not to test
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const std::vector<std::string> do_not_test {
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// Unallocated encodings are invalid.
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"UnallocatedEncoding",
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// Unimplemented in QEMU
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"STLLR",
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// Unimplemented in QEMU
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"LDLAR",
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};
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for (const auto& [fn, bitstring] : list) {
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if (std::strcmp(fn, "UnallocatedEncoding") == 0) {
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if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
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InstructionGenerator::AddInvalidInstruction(bitstring);
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continue;
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}
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