A64: PSTATE access and tests
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23f3afe0b3
commit
e8bcf72ee5
6 changed files with 86 additions and 2 deletions
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@ -83,6 +83,11 @@ public:
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/// Modify FPCR.
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void SetFpcr(std::uint32_t value);
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/// View PSTATE
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std::uint32_t GetPstate() const;
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/// Modify PSTATE
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void SetPstate(std::uint32_t value);
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/**
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* Returns true if Jit::Run was called but hasn't returned yet.
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* i.e.: We're in a callback.
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@ -128,7 +128,8 @@ void A64EmitX64::EmitA64SetNZCV(A64EmitContext& ctx, IR::Inst* inst) {
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Xbyak::Reg32 to_store = ctx.reg_alloc.UseGpr(args[0]).cvt32();
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code->and_(to_store, 0b11000001'00000001);
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code->imul(to_store, to_store, 0b00010000'00100001);
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code->and_(to_store, 0xFF000000);
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code->shl(to_store, 16);
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code->and_(to_store, 0xF0000000);
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code->mov(dword[r15 + offsetof(A64JitState, CPSR_nzcv)], to_store);
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}
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@ -125,6 +125,14 @@ public:
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jit_state.SetFpcr(value);
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}
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u32 GetPstate() const {
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return jit_state.GetPstate();
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}
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void SetPstate(u32 value) {
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jit_state.SetPstate(value);
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}
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bool IsExecuting() const {
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return is_executing;
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}
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@ -257,6 +265,14 @@ void Jit::SetFpcr(u32 value) {
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impl->SetFpcr(value);
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}
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u32 Jit::GetPstate() const {
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return impl->GetPstate();
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}
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void Jit::SetPstate(u32 value) {
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impl->SetPstate(value);
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}
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bool Jit::IsExecuting() const {
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return impl->IsExecuting();
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}
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@ -33,6 +33,12 @@ struct A64JitState {
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u32 CPSR_nzcv = 0;
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u32 FPSCR_nzcv = 0;
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u32 GetPstate() const {
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return CPSR_nzcv;
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}
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void SetPstate(u32 new_pstate) {
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CPSR_nzcv = new_pstate & 0xF0000000;
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}
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alignas(16) std::array<u64, 64> vec{}; // Extension registers.
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@ -124,6 +124,7 @@ bool Inst::WritesToCPSR() const {
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case Opcode::A32OrQFlag:
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case Opcode::A32SetGEFlags:
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case Opcode::A32SetGEFlagsCompressed:
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case Opcode::A64SetNZCV:
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return true;
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default:
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@ -387,7 +388,7 @@ void Inst::Use(const Value& value) {
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break;
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case Opcode::GetNZCVFromOp:
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ASSERT_MSG(!value.GetInst()->nzcv_inst, "Only one of each type of pseudo-op allowed");
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ASSERT_MSG(MayGetNZCVFromOp(), "This instruction doesn't support the GetNZCVFromOp pseduo-op");
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ASSERT_MSG(value.GetInst()->MayGetNZCVFromOp(), "This value doesn't support the GetNZCVFromOp pseduo-op");
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value.GetInst()->nzcv_inst = this;
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break;
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default:
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@ -113,3 +113,58 @@ TEST_CASE("A64: Bitmasks", "[a64]") {
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REQUIRE(jit.GetRegister(2) == 1);
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REQUIRE(jit.GetPC() == 12);
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}
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TEST_CASE("A64: ANDS NZCV", "[a64]") {
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TestEnv env;
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Dynarmic::A64::Jit jit{Dynarmic::A64::UserConfig{&env}};
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env.code_mem[0] = 0x6a020020; // ANDS W0, W1, W2
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env.code_mem[1] = 0x14000000; // B .
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SECTION("N=1, Z=0") {
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jit.SetRegister(0, 0);
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jit.SetRegister(1, 0xFFFFFFFF);
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jit.SetRegister(2, 0xFFFFFFFF);
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetRegister(0) == 0xFFFFFFFF);
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REQUIRE(jit.GetRegister(1) == 0xFFFFFFFF);
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REQUIRE(jit.GetRegister(2) == 0xFFFFFFFF);
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REQUIRE(jit.GetPC() == 4);
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REQUIRE((jit.GetPstate() & 0xF0000000) == 0x80000000);
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}
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SECTION("N=0, Z=1") {
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jit.SetRegister(0, 0);
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jit.SetRegister(1, 0xFFFFFFFF);
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jit.SetRegister(2, 0x00000000);
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetRegister(0) == 0x00000000);
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REQUIRE(jit.GetRegister(1) == 0xFFFFFFFF);
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REQUIRE(jit.GetRegister(2) == 0x00000000);
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REQUIRE(jit.GetPC() == 4);
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REQUIRE((jit.GetPstate() & 0xF0000000) == 0x40000000);
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}
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SECTION("N=0, Z=0") {
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jit.SetRegister(0, 0);
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jit.SetRegister(1, 0x12345678);
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jit.SetRegister(2, 0x7324a993);
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jit.SetPC(0);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetRegister(0) == 0x12240010);
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REQUIRE(jit.GetRegister(1) == 0x12345678);
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REQUIRE(jit.GetRegister(2) == 0x7324a993);
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REQUIRE(jit.GetPC() == 4);
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REQUIRE((jit.GetPstate() & 0xF0000000) == 0x00000000);
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}
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}
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