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A64: Implement AND (vector)

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This commit is contained in:
MerryMage 2018-01-21 18:27:06 +00:00
parent 35aaee6cc6
commit f81d0a2536
6 changed files with 25 additions and 1 deletions
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5
src/backend_x64/emit_x64.cpp
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@ -2199,6 +2199,11 @@ void EmitX64<JST>::EmitVectorAdd64(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::paddq);
}
template <typename JST>
void EmitX64<JST>::EmitVectorAnd(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pand);
}
template <typename JST>
static void DenormalsAreZero32(BlockOfCode* code, Xbyak::Xmm xmm_value, Xbyak::Reg32 gpr_scratch) {
Xbyak::Label end;

2
src/frontend/A64/decoder/a64.inc
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@ -832,7 +832,7 @@ INST(ADD_vector, "ADD (vector)", "0Q001
//INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
//INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd")
//INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd")
//INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")
//INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")

13
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -35,5 +35,18 @@ bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd)
return true;
}
bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
auto operand1 = V(datasize, Vn);
auto operand2 = V(datasize, Vm);
auto result = ir.VectorAnd(operand1, operand2);
V(datasize, Vd, result);
return true;
}
} // namespace A64
} // namespace Dynarmic

4
src/frontend/ir/ir_emitter.cpp
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@ -620,6 +620,10 @@ U128 IREmitter::VectorAdd64(const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorAdd64, a, b);
}
U128 IREmitter::VectorAnd(const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorAnd, a, b);
}
U32 IREmitter::FPAbs32(const U32& a) {
return Inst<U32>(Opcode::FPAbs32, a);
}

1
src/frontend/ir/ir_emitter.h
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@ -181,6 +181,7 @@ public:
U128 VectorAdd16(const U128& a, const U128& b);
U128 VectorAdd32(const U128& a, const U128& b);
U128 VectorAdd64(const U128& a, const U128& b);
U128 VectorAnd(const U128& a, const U128& b);
U32 FPAbs32(const U32& a);
U64 FPAbs64(const U64& a);

1
src/frontend/ir/opcodes.inc
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@ -164,6 +164,7 @@ OPCODE(VectorAdd8, T::U128, T::U128, T::U128
OPCODE(VectorAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd64, T::U128, T::U128, T::U128 )
OPCODE(VectorAnd, T::U128, T::U128, T::U128 )
// Floating-point operations
OPCODE(FPAbs32, T::U32, T::U32 )