MerryMage
dd88cee15a
translate/impl: Add Vpart
2020-04-22 20:46:13 +01:00
MerryMage
cc9efd13c9
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
2020-04-22 20:46:13 +01:00
MerryMage
81713c2b77
A64: Implement FCCMPE
2020-04-22 20:46:13 +01:00
MerryMage
ef906dbbfa
A64: Implement FCCMP
2020-04-22 20:46:13 +01:00
MerryMage
aac5af50e2
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2020-04-22 20:46:13 +01:00
Lioncash
2ee39d6b36
A64: Implement FMOV (register)
2020-04-22 20:46:13 +01:00
MerryMage
b02b861242
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
2020-04-22 20:46:13 +01:00
Lioncash
5a65313236
A64: Implement CCMP (immediate)
2020-04-22 20:46:13 +01:00
Lioncash
ab4664de61
A64: Implement CCMN (immediate)
2020-04-22 20:46:13 +01:00
Lioncash
a6c6539109
A64: Implement CCMP (register)
2020-04-22 20:46:13 +01:00
Lioncash
22632db337
microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
2020-04-22 20:46:13 +01:00
MerryMage
c5033b5dda
A64: Implement CCMN (register)
2020-04-22 20:46:13 +01:00
MerryMage
dd2a6684fe
IR: Add ConditionalSelectNZCV instruction
2020-04-22 20:46:13 +01:00
MerryMage
4491746eae
A64: Implement FNEG
2020-04-22 20:46:13 +01:00
MerryMage
db958061a3
A64: Implement FABS
2020-04-22 20:46:13 +01:00
MerryMage
8765b421b7
A64: Implement FCSEL
2020-04-22 20:46:13 +01:00
MerryMage
7e82d8eede
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
2020-04-22 20:46:13 +01:00
MerryMage
2409e5d082
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
2020-04-22 20:46:13 +01:00
MerryMage
56bc7825ef
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
2020-04-22 20:46:13 +01:00
Lioncash
40614202e7
A64: Implement AESD
2020-04-22 20:46:13 +01:00
Lioncash
ccef85dbb7
A64: Implement AESE
2020-04-22 20:46:13 +01:00
MerryMage
8931ee346b
IR: Add IR instruction NZCVFromPackedFlags
...
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2020-04-22 20:46:13 +01:00
MerryMage
0bb4474fb9
A64: Implement INS (general)
2020-04-22 20:46:13 +01:00
MerryMage
d13704fdef
A64: Implement INS (element)
2020-04-22 20:46:13 +01:00
MerryMage
0642d49919
A64: Implement SMOV
2020-04-22 20:46:13 +01:00
MerryMage
5297027ebe
A64: Implement UMOV
2020-04-22 20:46:13 +01:00
MerryMage
47661b746b
basic_block: Fix bogus GCC maybe-uninitialized warning
2020-04-22 20:46:13 +01:00
MerryMage
1fb0957aa3
A64: Implement FCVT
2020-04-22 20:46:13 +01:00
MerryMage
ca38225e08
fuzz_with_unicorn: Skip instructions that need to be interpreted
2020-04-22 20:46:13 +01:00
MerryMage
4be55b8b84
A64: Implement FMOV (scalar, immediate)
2020-04-22 20:46:13 +01:00
MerryMage
a07c05ea51
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
2020-04-22 20:46:13 +01:00
MerryMage
93fcbdf1e2
A64: Implement FCMP, FCMPE
2020-04-22 20:46:13 +01:00
MerryMage
99d8ebe4d5
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
2020-04-22 20:46:13 +01:00
MerryMage
429dc24587
IR: Merge U32 and U64 variants of FP instructions
2020-04-22 20:46:13 +01:00
MerryMage
ed2bedec43
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2020-04-22 20:46:13 +01:00
MerryMage
ebfc51c609
IR: Implement VectorSetElement{8,16,32,64}
2020-04-22 20:46:13 +01:00
Lioncash
a5c4fbc783
A64: Implement AESIMC and AESMC
2020-04-22 20:46:13 +01:00
Lioncash
af1384d700
A64: Implement CRC32
2020-04-22 20:46:12 +01:00
MerryMage
cc0eb18a0b
A32: data_processing: Remove !S assertions
2020-04-22 20:46:12 +01:00
MerryMage
865a30eb0d
A32: Implement BKPT
2020-04-22 20:46:12 +01:00
MerryMage
f023bbb893
A32: Add ExceptionRaised IR instruction and use it
2020-04-22 20:46:12 +01:00
Lioncash
7ffbebf290
A64: Implement CRC32C
2020-04-22 20:46:12 +01:00
MerryMage
d7044bc751
assert: Use fmt in ASSERT_MSG
2020-04-22 20:46:12 +01:00
MerryMage
52268298a8
a64_emit_x64: Perform RSB predictions
2020-04-22 20:46:12 +01:00
MerryMage
98ec9c5f90
A32: Change UserCallbacks to be similar to A64's interface
2020-04-22 20:46:12 +01:00
MerryMage
6fc228f7fd
ir_opt: Add A64 Get/Set Elimination Pass
2020-04-22 20:46:12 +01:00
MerryMage
e01b500aea
ir_emitter: Allow the insertion point for new instructions to be set
2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050
A64: Implement EXTR
2020-04-22 20:46:12 +01:00
MerryMage
88ae7fce52
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
2020-04-22 20:44:38 +01:00
MerryMage
b513b2ef05
IR: Implement IR instructions A64{Get,Set}S
2020-04-22 20:44:38 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
...
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
Lioncash
7abd673a49
A64: Zero upper 64 bits in ORN if using the 64-bit variant
...
Resolves a TODO
2020-04-22 20:44:38 +01:00
MerryMage
ba3d6da0c8
load_store_register_unprivileged: bug: LDTRSW
2020-04-22 20:44:38 +01:00
MerryMage
75756137c6
A64: Implement CMEQ (register, vector)
2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions ( #142 )
2020-04-22 20:44:38 +01:00
MerryMage
94383fd934
microinstruction: Missed A64{Read,Write}Memory128 from opcode information
2020-04-22 20:44:38 +01:00
James Rowe
589ad7232f
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
2020-04-22 20:44:38 +01:00
James Rowe
ae880d8391
A64: Fix bugs and address review comments
2020-04-22 20:44:38 +01:00
James Rowe
3aeb7ca50c
Add missing returns
2020-04-22 20:44:38 +01:00
James Rowe
41e6e659c5
A64: Implement Load/Store register (unprivileged)
2020-04-22 20:44:37 +01:00
MerryMage
285fd22c30
IR: Add IR instruction VectorZeroUpper
2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806
Implemented SDIV and UDIV instructions
2020-04-22 20:44:37 +01:00
MerryMage
6033b05ca6
A64: Implement LDR/STR (immediate, SIMD&FP)
2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621
IR: Add IR instructions A64Memory{Read,Write}128
...
This implementation only works on macOS and Linux.
2020-04-22 20:44:37 +01:00
MerryMage
e00a522cba
IR: Add IR instruction VectorGetElement{8,16,32,64}
2020-04-22 20:44:37 +01:00
MerryMage
28ccd85e5c
IR: Add IR instruction ZeroExtendToQuad
2020-04-22 20:44:37 +01:00
MerryMage
3caf192f60
A64: Implement DUP (general)
2020-04-22 20:44:37 +01:00
MerryMage
793753bf63
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
2020-04-22 20:44:37 +01:00
Lioncash
8ee854232c
General: Default constructors and destructors where applicable
2020-04-22 20:44:37 +01:00
Lioncash
d1e4526e1c
ir_emitter: Remove unused includes
2020-04-22 20:44:37 +01:00
Lioncash
6f9216d544
A64: Implement RBIT
2020-04-22 20:44:37 +01:00
MerryMage
9b0a21915f
ir_emitted: Remove unimplemented IR instruction Unimplemented
2020-04-22 20:44:37 +01:00
MerryMage
d4b05b28cf
A64: Implement CLS
...
This is not the cleanest implementation.
2020-04-22 20:42:46 +01:00
MerryMage
b8e26bfdc3
A64: Implement ADDP (vector)
2020-04-22 20:42:46 +01:00
MerryMage
eaf545877a
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
2020-04-22 20:42:46 +01:00
MerryMage
394bd57bb6
microinstruction: bug: Add missing opcodes
2020-04-22 20:42:46 +01:00
Lioncash
bb1c5bd3b2
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
2020-04-22 20:42:46 +01:00
Lioncash
c1a25bfc2f
A64: Implement MADD and MSUB
2020-04-22 20:42:46 +01:00
Lioncash
b7c5055d42
A64: Implement CLZ
2020-04-22 20:42:46 +01:00
Lioncash
b612782445
opcodes: Add 64-bit CountLeadingZeroes opcode
2020-04-22 20:42:46 +01:00
MerryMage
4c4efb2213
data_processing_register: Clean-up
2020-04-22 20:42:46 +01:00
Lioncash
ae5dbcbed6
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
...
Truly the most difficult A64 instructions to implement.
2020-04-22 20:42:46 +01:00
Lioncash
4d8f4aa8af
A64: Implement ASRV, LSLV, LSRV, and RORV
2020-04-22 20:42:46 +01:00
Lioncash
a8a65beb2b
data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG
2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536
A64: Implement AND (vector)
2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
Thomas Guillemard
896cf44f96
A64: Implement REV, REV32, and REV16 ( #126 )
2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc
reg_alloc: Consider bitwidth of data and registers when emitting instructions
2020-04-22 20:42:46 +01:00
MerryMage
144b629d8a
A64: Implement CSEL
2020-04-22 20:42:45 +01:00
MerryMage
6395f09f94
IR: Implement Conditional Select
2020-04-22 20:42:45 +01:00
MerryMage
19da68568e
A64/translate/branch: bug: Read-after-write error in BLR
2020-04-22 20:42:45 +01:00
MerryMage
9f57283a30
A64: Implement SBFM, BFM, UBFM
2020-04-22 20:42:45 +01:00
MerryMage
cdbc8d07a5
A64: Implement MOVN, MOVZ, MOVK
2020-04-22 20:42:45 +01:00
MerryMage
ecebe14a01
ir/location_descriptor: Add missing <functional> header for std::hash
2020-04-22 20:42:45 +01:00
MerryMage
c6a091d874
A64: Optimization: Merge interpret blocks
2020-04-22 20:42:45 +01:00
MerryMage
21fe61eac6
A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
2020-04-22 20:42:45 +01:00
MerryMage
7c4b70751c
A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
2020-04-22 20:42:45 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
61125d6dd1
A64/translate: Add TranslateSingleInstruction function
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
a1dfa01515
imm: Suppress MSVC warning C4244: value will never be truncated
2020-04-22 20:42:45 +01:00
MerryMage
26da149639
imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions
2020-04-22 20:42:45 +01:00
MerryMage
b34c6616d4
A64/decoder: Split decoder data from header
2020-04-22 20:42:45 +01:00
MerryMage
595f157e5e
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
511215342b
A64/location_descriptor: Fix -fpermissive warning on GCC
2020-04-22 20:42:45 +01:00
MerryMage
243f06c613
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
25411da838
A32: Implement load stores (immediate)
2020-04-22 20:42:45 +01:00
MerryMage
2aadeec291
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
9e27e4d250
imm: bug: SignExtend wasn't working for T with bit size > 32
2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48
A64: Implement compare and branch
2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5
A64: PSTATE access and tests
2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3
A64: Implement branch (register)
2020-04-22 20:42:45 +01:00
MerryMage
86d1095df7
A64: Implement branch
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
5a1d88c5dc
A64: Implement pcrel
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93
A64: Backend framework
2020-04-22 20:42:44 +01:00
MerryMage
e161cf16f5
A64: Initial framework
2020-04-22 20:42:44 +01:00
MerryMage
f61da0b5a9
IR: Compile-time type-checking of IR
2020-04-22 20:39:27 +01:00
MerryMage
44f7f04b5c
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2020-04-22 20:39:27 +01:00
MerryMage
83022322d1
Make IR->A32 LocationDescriptor conversion explicit
2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1
Final A32 refactor
2020-04-22 20:39:27 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
MerryMage
4393473d06
interface: Allow saving and storing of contexts
2020-04-22 20:26:40 +01:00
MerryMage
19a7fb8992
jit_state: Split off CPSR.NZCV
2020-04-22 20:26:40 +01:00
MerryMage
311361b409
jit_state: Split off CPSR.{E,T}
...
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72
emit_x64: Use boost::icl::interval_map to speed up ranged invalidation
2020-04-22 20:26:40 +01:00
MerryMage
80c56aa89d
Remove unnecessary use of boost::make_optional
...
Closes #119 .
2020-04-22 20:26:12 +01:00
MerryMage
de6a93a160
decoder_detail: Lambda captures may be unused if iota is an empty sequence
...
Closes #120
2020-04-22 20:26:12 +01:00
MerryMage
3141dadea9
Remove UNUSED macro
2020-04-22 20:26:12 +01:00
MerryMage
7cac9519b0
microinstruction: Remove DecrementRemainingUses
2020-04-22 20:26:12 +01:00
MerryMage
5d72f7048f
basic_block: Add inst address and use count to DumpBlock
...
This additional output assists with debugging.
2020-04-22 20:26:12 +01:00
MerryMage
d1e0a29cd9
Implement IR instruction PackedSelect, reimplement SEL
2020-04-22 20:26:07 +01:00
MerryMage
814e378249
VCMP and VCMPE were the other way around
...
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
2020-04-22 20:26:07 +01:00
MerryMage
29471be317
Standardize location of storage-class specifiers: Place at beginning of declarations
...
Justification: C99 specifies that doing otherwise is an obsolescent feature.
2017-09-29 01:23:45 +01:00
MerryMage
993e142c6b
disassembler: Fix RegList
2017-08-05 01:57:29 +01:00
MerryMage
6197bde0fc
disassembler_arm: Fix disassembly of LDRH (reg)
2017-07-30 18:45:55 +01:00
MerryMage
599a613fea
Move SEL from status_register_access to misc
2017-04-25 13:57:27 +01:00
MerryMage
50bb317104
parallel: UQADD8 and UQADD16 are unpredictable when {d|n|m} == 15
2017-04-25 13:45:31 +01:00
MerryMage
7639dfea51
coprocessor: Use && instead of & with boolean arguments
2017-04-22 15:05:31 +01:00
MerryMage
1c21ae6bcd
saturated: Implement QASX, QSAX, UQASX, UQSAX
2017-04-10 10:21:51 +01:00
MerryMage
523ae542f4
microinstruction: Implement HasAssociatedPseudoOperation
2017-04-04 13:10:50 +01:00
MerryMage
05e97058c3
parallel: Add and Subtract with Exchange improvements
...
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8
Ranged cache invalidation
2017-03-20 11:58:25 +00:00
MerryMage
92a01b0cd8
Prefer ASSERT to DEBUG_ASSERT
2017-02-26 23:30:40 +00:00
MerryMage
bbeea72eba
ir_opt: Remove redundant shift instructions
2017-02-26 15:28:14 +00:00
MerryMage
4ed8ee7489
microinstruction: Void arguments when invalidating instruction
2017-02-18 21:29:23 +00:00
MerryMage
7fa5845c1f
extension: Implement SXTAB16 and SXTB16
2017-02-18 20:14:44 +00:00
MerryMage
73d1cf36c3
extension: Simplify UXTB16
2017-02-18 20:14:39 +00:00
MerryMage
6edcfeba0b
extension: Simplify rotation code
2017-02-18 20:14:37 +00:00
MerryMage
cc9d2c4603
saturated: Implement SSAT16 and USAT16
2017-02-18 17:43:57 +00:00
MerryMage
358cf7c322
vfp: Implement vectorized VFP instructions
2017-02-18 01:13:25 +00:00
MerryMage
f2dd82967f
load_store: Simplify implementation
...
* Remove dead code
* Standardise code style with rest of code base
2017-02-16 22:28:56 +00:00
MerryMage
5a20a37d3f
arm/fpscr: Correct Stride implementation
2017-02-11 12:13:57 +00:00
MerryMage
033e8b9b1e
vfp: Rename variables a, b, c to more sensible names
2017-02-06 21:14:36 +00:00
MerryMage
642ccb0f66
ir/value: Support U16 immediates
2017-01-29 22:58:11 +00:00
MerryMage
5f7ffe0d0b
microinstruction: Implement Inst::AreAllArgsImmediates
2017-01-29 22:56:59 +00:00
MerryMage
22804dc6a5
microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const
2017-01-29 22:53:46 +00:00
MerryMage
1d4446cad5
microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith
2017-01-29 22:52:33 +00:00
MerryMage
e3bc7d039f
Implement CDP, LDC, MCR, MCRR, MRC, MRRC, STC
2017-01-08 14:56:06 +00:00
MerryMage
48693eb6ff
Implement coprocessor-related microinstructions
...
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
2017-01-08 14:56:06 +00:00
MerryMage
b3ae57619d
types: Formatting for CoprogReg
2017-01-08 14:56:06 +00:00
MerryMage
d8a37e287c
IR: Add IR type CoprocInfo
2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d
IR: Remove unused microinstructions NegateLowWord and NegateHighWord
2017-01-05 20:16:39 +00:00
Fernando Sahmkow
70f4235ee9
Implement UXTAB16 ( #78 )
2016-12-29 12:15:18 +00:00
FernandoS27
d5610eb26c
Implement UHASX, UHSAX, SHASX and SHSAX ( #75 )
2016-12-28 21:32:22 +00:00
MerryMage
e9df248d56
decoder_detail: Support const member functions
2016-12-23 11:33:40 +00:00
MerryMage
b1bad4b5cc
decoder_detail: static_assert member function is from visitor class
...
Improves readability of compiler errors.
2016-12-23 11:10:02 +00:00
MerryMage
c78f153ddb
decoder/arm: Sort decoders according to number of bits in mask
2016-12-22 15:25:38 +00:00
MerryMage
cb38c94b58
decoder/arm: Fix decoding of RFE
2016-12-22 15:25:07 +00:00
MerryMage
7e77ee7fd6
decoder/arm: Fix decoding of MCR2
2016-12-22 15:11:47 +00:00
Fernando Sahmkow
677f62dd6f
Implement SHSUB8 and SHSUB16 ( #74 )
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* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
MerryMage
967f3cf7e1
Implement CPS (Thumb)
...
* Since currently only User mode is emulated, CPS is a NOP.
2016-12-21 22:44:27 +00:00
MerryMage
c764a2b889
Implement MUL (T1)
2016-12-21 22:44:14 +00:00
MerryMage
36082087de
callbacks: Read code using MemoryReadCode callback
2016-12-21 21:39:14 +00:00
MerryMage
56ea2386d3
saturated: Implement SSAT and USAT
2016-12-21 19:51:25 +00:00
MerryMage
6a269a6ebd
IR: Add microinstructions UnsignedSaturation and SignedSaturation
2016-12-21 19:51:25 +00:00
FernandoS27
8919265d2c
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245
Implemented USAD8 and USADA8
2016-12-20 21:52:38 +00:00
MerryMage
96e46ba6b5
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:34:29 +00:00
MerryMage
b178ab3bec
Replace (void)(...); idiom with UNUSED macro
2016-12-15 21:36:05 +00:00
MerryMage
df197ff6b1
arm/types: Use smallest possible standard type that has sufficient bits for Imm{} types
2016-12-15 20:52:21 +00:00
MerryMage
546198d603
translate_arm: Mark arguments as unused
2016-12-15 20:52:20 +00:00
MerryMage
8d5522f4a0
dissassembler_arm: Support BKPT, QASX, QSAX, UQASX, UQSAX
2016-12-15 20:16:08 +00:00
MerryMage
52e1445f43
Implement USUB8
2016-12-05 00:29:15 +00:00
MerryMage
5c1aab1666
Implement CLZ
...
Includes tests
2016-12-04 22:56:33 +00:00
MerryMage
1a1646d962
Implement UADD8
2016-12-04 20:52:33 +00:00
MerryMage
7cad6949e7
IR: Implement new pseudo-operation GetGEFromOp
2016-12-04 20:52:06 +00:00
MerryMage
e166965f3e
Implement VCMP
2016-12-03 11:41:09 +00:00
MerryMage
f2fe376fc6
Support 64-bit immediates
2016-12-03 11:29:50 +00:00
Mat M
de1f831d79
microinstruction: Make use_count private ( #53 )
...
Makes the operation a part of the direct interface.
2016-11-30 21:51:06 +00:00
Merry
0ff8c375af
Implement UHSUB8 and UHSUB16 ( #48 )
2016-11-26 18:27:21 +00:00
Merry
cb17f9a3ed
Implement SHADD8 and SHADD16 ( #47 )
2016-11-26 18:12:29 +00:00
Sebastian Valle
11ae8d1ffa
Added disassembler support for the ARM parallel add/subtract (modulo arithmetic) instructions. ( #50 )
2016-11-26 17:58:09 +00:00
Sebastian Valle
ed71e31cea
Added disassembler support for the ARM parallel and saturated instructions ( #44 )
2016-11-26 17:49:46 +00:00
MerryMage
c0c1bb1094
Implemented UHADD16
2016-11-26 11:28:20 +00:00
Yuri Kunde Schlesner
9ec51f74bd
libfmt: Update version to current master
2016-11-25 20:47:04 +00:00
Sebastian Valle
4d44474ad4
Implemented the ARM UHADD8 instruction. ( #45 )
...
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
2016-11-25 20:32:22 +00:00
Sebastian Valle
f32921d493
ARM: Implemented UXTB16. ( #42 )
...
It passes tests.
2016-11-24 08:21:12 +00:00
Sebastian Valle
32615d0eff
Implemented the PKHTB and PKHBT instructions with tests. ( #40 )
2016-11-23 21:45:18 +00:00
MerryMage
780ff8e00e
status_register_access: SEL: Use GetGEFlags
2016-11-23 19:47:35 +00:00
MerryMage
b6f7b8babd
ir: Implement GetGEFlags, SetGEFlags
2016-11-23 19:44:27 +00:00
Sebastian Valle
d589c63107
Implemented the ARM SEL instruction, with tests. ( #39 )
...
The test for this instruction is very peculiar. As the instruction's behavior depends on the value of the CPSR, we generate a MSR instruction after each SEL instruction to change the CPSR.
2016-11-23 18:14:07 +00:00
Mat M
65dcf45ca6
FPSCR: Mask away reserved bits ( #34 )
2016-09-21 17:51:13 +01:00
MerryMage
792f2bfd94
translate_arm: Remove unused method ArmTranslatorVisitor::LinkToNextInstruction
2016-09-21 14:07:53 +01:00
Mat M
f75acd6cfb
decoder: Generify the matcher interface ( #33 )
...
Gets rid of a bit of duplication while remaining compatible
with the current interfaces in place.
2016-09-17 09:48:18 +01:00
Mat M
943487ecee
disassembler: Provide includes to function declarations ( #32 )
2016-09-14 23:03:09 +01:00
Mat M
72897b5def
types: Provide ostream operator<< overloads where applicable ( #30 )
2016-09-07 14:21:17 +01:00
Mat M
6a2174ebfa
Add missing explicit specifiers ( #27 )
2016-09-07 12:08:48 +01:00
Mat M
6e0f27a500
types: Add helpers for determining single and doubleword extension registers ( #26 )
2016-09-07 12:08:35 +01:00
Mat M
5bc9ce544f
arm_types: Move into arm folder ( #25 )
2016-09-06 00:52:33 +01:00
Mat M
b40d19c3b7
location_descriptor: Provide operator<< string overload ( #24 )
2016-09-05 21:31:25 +01:00
Mat M
6d53bb6d7e
arm_types: Split out LocationDescriptor ( #20 )
...
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
2016-09-05 11:54:09 +01:00
Mat M
84336cf29d
value: Change Value into a class ( #19 )
...
'struct' is a little bit of a misnomer, considering it has invariants
2016-09-05 11:53:56 +01:00
Mat M
858796a029
Eliminate variable shadowing warnings with MSVC ( #17 )
2016-09-04 11:30:57 +01:00
Mat M
7f9a0c3c38
Remove unnecessary explicit includes ( #16 )
2016-09-03 21:48:03 +01:00
Mat M
05b189bc26
arm_types: Specialize std::hash for LocationDescriptor ( #14 )
...
Same thing, but with the benefit of working with anything that uses
std::hash by default.
2016-09-03 12:48:47 +01:00
Mat M
8c4df46580
FPSCR: Make value constructor explicit ( #13 )
...
Maintains consistency between the PSR helper.
2016-09-03 12:48:31 +01:00
Mat M
5aa4f753b6
load_store: Add checks for unpredictability to other singular store instructions ( #11 )
2016-09-02 21:10:28 +01:00
Mat M
6ec651498d
arm: Add PSR helper type ( #3 )
2016-09-02 17:34:33 +01:00
Mat M
00d0f4d5ff
load_store: Add correctness checks for STRD variants ( #7 )
...
STRD doesn't allow the use of the PC in either Rt or Rt2
2016-09-02 17:32:02 +01:00
MerryMage
ba04be5071
travis: Build on OS X
2016-09-02 17:08:09 +01:00
MerryMage
b3743e9453
Revert "arm_types: Don't use std::hash<u64>() for LocationDescriptorHash"
...
This reverts commit 519c714dbc
2016-09-02 14:33:56 +01:00
MerryMage
519c714dbc
arm_types: Don't use std::hash<u64>() for LocationDescriptorHash
...
Apple Clang (clang-600.0.54 on x86_64-apple-darwin13.4.0) complains with:
implicit instantiation of undefined template 'std::__1::hash<unsigned long long>'
2016-09-02 12:45:09 +01:00
Mat M
a465b2ddbc
ir_emitter: Fix typo. ClearExlcusive -> ClearExclusive ( #5 )
2016-09-02 12:17:22 +01:00
Mat M
ea157dfd52
translate_arm: const-correctness ( #6 )
2016-09-02 12:17:02 +01:00
Mat M
7e3c981974
translate: Forward declare LocationDescriptor ( #2 )
2016-09-01 09:46:35 +01:00
MerryMage
dca3b2f079
Implement VMRS and VMSR
2016-08-26 22:47:54 +01:00
Lioncash
0102951bdd
Convert formatting over to fmtlib
2016-08-26 13:13:19 +01:00
MerryMage
4322c0907c
microinstruction: Rename FindUseWithOpcode to GetAssociatedPseudoOperation, encapsulate associated variables
2016-08-25 21:08:47 +01:00
MerryMage
30df51c2dc
ir_emitter: Should be in the IR namespace, not the Arm namespace
2016-08-25 17:36:42 +01:00
MerryMage
922d1fd198
Merge branch 'xbyak'
2016-08-25 16:54:48 +01:00
MerryMage
e32812cd00
Port x64 backend to xbyak
2016-08-25 16:18:17 +01:00
Lioncash
0e12fb6a56
basic_block: Move all variables behind a public interface
2016-08-25 16:14:37 +01:00
Lioncash
1d8432487d
arm_types: Provide the not-equals operator overload for LocationDescriptor
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Generally if == has an overload, != should be provided for symmetry.
2016-08-25 14:08:16 +01:00
MerryMage
dc26afbd7e
translate_arm: Translate more than one conditional instruction in a block
2016-08-25 13:05:33 +01:00
MerryMage
aa9b63bac4
basic_block: DumpBlock now dumps terminal details
2016-08-25 13:01:32 +01:00
Lioncash
37755cbfec
translate: Simplify function pointer calls
...
They can just be called like regular functions
2016-08-24 23:19:50 +01:00
Lioncash
eba3a06d80
frontend: Introduce FPSCR register helper class
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Encapsulates all of the FPSCR state.
2016-08-24 20:51:14 +01:00
MerryMage
b5a86889cd
Implement VCVT
2016-08-23 22:20:04 +01:00
MerryMage
78464a8f01
translate_arm/vfp2: Implement VSTM (A1, A2)
2016-08-23 20:54:38 +01:00
MerryMage
a96704eb0f
arm_types: new_reg >= 0 is always true since new_reg is unsigned
2016-08-23 20:11:41 +01:00
MerryMage
7a01dba3c4
arm_types: Change type signature of operator+ to size_t instead of int
2016-08-23 20:07:53 +01:00
MerryMage
af9a68f0d1
translate_arm/vfp2: Implement VLDM (A1, A2)
2016-08-23 20:07:06 +01:00
