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A64: Implement SUB (vector), scalar variant

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This commit is contained in:
MerryMage 2018-02-06 22:12:39 +00:00
parent 4c5871d5d5
commit ea69cb4474
2 changed files with 15 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -505,7 +505,7 @@ INST(ADD_1, "ADD (vector)", "01011
//INST(UQSHL_reg_1, "UQSHL (register)", "01111110zz1mmmmm010011nnnnnddddd")
//INST(URSHL_1, "URSHL", "01111110zz1mmmmm010101nnnnnddddd")
//INST(UQRSHL_1, "UQRSHL", "01111110zz1mmmmm010111nnnnnddddd")
//INST(SUB_1, "SUB (vector)", "01111110zz1mmmmm100001nnnnnddddd")
INST(SUB_1, "SUB (vector)", "01111110zz1mmmmm100001nnnnnddddd")
//INST(CMEQ_reg_1, "CMEQ (register)", "01111110zz1mmmmm100011nnnnnddddd")
//INST(SQRDMULH_vec_1, "SQRDMULH (vector)", "01111110zz1mmmmm101101nnnnnddddd")

14
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
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@ -23,4 +23,18 @@ bool TranslatorVisitor::ADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = esize;
const IR::U64 operand1 = V_scalar(datasize, Vn);
const IR::U64 operand2 = V_scalar(datasize, Vm);
const IR::U64 result = ir.Sub(operand1, operand2);
V_scalar(datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64