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assert: Use fmt in ASSERT_MSG

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This commit is contained in:
MerryMage 2018-01-27 23:42:30 +00:00
parent b60c7f31c1
commit d7044bc751
17 changed files with 68 additions and 38 deletions
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4
src/backend_x64/a32_emit_x64.cpp
View file

@ -7,6 +7,8 @@
#include <unordered_map>
#include <unordered_set>
#include <fmt/ostream.h>
#include <dynarmic/A32/coprocessor.h>
#include "backend_x64/a32_emit_x64.h"
@ -108,7 +110,7 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) {
#undef A64OPC
default:
ASSERT_MSG(false, "Invalid opcode %zu", static_cast<size_t>(inst->GetOpcode()));
ASSERT_MSG(false, "Invalid opcode: {}", inst->GetOpcode());
break;
}

4
src/backend_x64/a64_emit_x64.cpp
View file

@ -7,6 +7,8 @@
#include <unordered_map>
#include <unordered_set>
#include <fmt/ostream.h>
#include "backend_x64/a64_emit_x64.h"
#include "backend_x64/a64_jitstate.h"
#include "backend_x64/abi.h"
@ -89,7 +91,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) {
#undef A64OPC
default:
ASSERT_MSG(false, "Invalid opcode %zu", static_cast<size_t>(inst->GetOpcode()));
ASSERT_MSG(false, "Invalid opcode: {}", inst->GetOpcode());
break;
}

2
src/backend_x64/emit_x64.cpp
View file

@ -240,7 +240,7 @@ Xbyak::Label EmitX64::EmitCond(IR::Cond cond) {
break;
}
default:
ASSERT_MSG(false, "Unknown cond %zu", static_cast<size_t>(cond));
ASSERT_MSG(false, "Unknown cond {}", static_cast<size_t>(cond));
break;
}

2
src/backend_x64/emit_x64_data_processing.cpp
View file

@ -162,7 +162,7 @@ static void EmitConditionalSelect(BlockOfCode* code, EmitContext& ctx, IR::Inst*
code->mov(else_, then_);
break;
default:
ASSERT_MSG(false, "Invalid cond %zu", static_cast<size_t>(args[0].GetImmediateCond()));
ASSERT_MSG(false, "Invalid cond {}", static_cast<size_t>(args[0].GetImmediateCond()));
}
ctx.reg_alloc.DefineValue(inst, else_);

3
src/backend_x64/reg_alloc.cpp
View file

@ -8,6 +8,7 @@
#include <numeric>
#include <utility>
#include <fmt/ostream.h>
#include <xbyak.h>
#include "backend_x64/abi.h"
@ -49,7 +50,7 @@ static size_t GetBitWidth(IR::Type type) {
case IR::Type::CoprocInfo:
case IR::Type::Cond:
case IR::Type::Void:
ASSERT_MSG(false, "Type %zu cannot be represented at runtime", static_cast<size_t>(type));
ASSERT_MSG(false, "Type {} cannot be represented at runtime", type);
return 0;
case IR::Type::Opaque:
ASSERT_MSG(false, "Not a concrete type");

10
src/common/assert.h
View file

@ -6,6 +6,8 @@
#include <cstdio>
#include <fmt/format.h>
// For asserts we'd like to keep all the junk executed when an assert happens away from the
// important code in the function. One way of doing this is to put all the relevant code inside a
// lambda and force the compiler to not inline it. Unfortunately, MSVC seems to have no syntax to
@ -26,14 +28,14 @@ static void assert_noinline_call(const Fn& fn) {
#define ASSERT(_a_) \
do if (!(_a_)) { assert_noinline_call([] { \
fprintf(stderr, "Assertion Failed!: %s\n", #_a_); \
fmt::print(stderr, "Assertion Failed!: {}\n", #_a_); \
}); } while (false)
#define ASSERT_MSG(_a_, ...) \
do if (!(_a_)) { assert_noinline_call([&] { \
fprintf(stderr, "Assertion Failed!: %s\n", #_a_); \
fprintf(stderr, "Message: " __VA_ARGS__); \
fprintf(stderr, "\n"); \
fmt::print(stderr, "Assertion Failed!: {}\n", #_a_); \
fmt::print(stderr, "Message: " __VA_ARGS__); \
fmt::print(stderr, "\n"); \
}); } while (false)
#define UNREACHABLE() ASSERT_MSG(false, "Unreachable code!")

8
src/frontend/A64/translate/impl/impl.cpp
View file

@ -164,7 +164,7 @@ IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*
case 16:
return ir.ReadMemory128(address);
default:
ASSERT_MSG(false, "Invalid bytesize parameter %zu", bytesize);
ASSERT_MSG(false, "Invalid bytesize parameter {}", bytesize);
return {};
}
}
@ -187,7 +187,7 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*acctype*
ir.WriteMemory128(address, value);
return;
default:
ASSERT_MSG(false, "Invalid bytesize parameter %zu", bytesize);
ASSERT_MSG(false, "Invalid bytesize parameter {}", bytesize);
return;
}
}
@ -199,7 +199,7 @@ IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
case 64:
return ir.SignExtendToLong(value);
default:
ASSERT_MSG(false, "Invalid size parameter %zu", to_size);
ASSERT_MSG(false, "Invalid size parameter {}", to_size);
return {};
}
}
@ -211,7 +211,7 @@ IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
case 64:
return ir.ZeroExtendToLong(value);
default:
ASSERT_MSG(false, "Invalid size parameter %zu", to_size);
ASSERT_MSG(false, "Invalid size parameter {}", to_size);
return {};
}
}

28
src/frontend/ir/opcodes.cpp
View file

@ -6,8 +6,13 @@
#include <array>
#include <map>
#include <ostream>
#include <string>
#include <vector>
#include <fmt/format.h>
#include <fmt/ostream.h>
#include "frontend/ir/opcodes.h"
namespace Dynarmic::IR {
@ -48,19 +53,32 @@ Type GetArgTypeOf(Opcode op, size_t arg_index) {
return OpcodeInfo::opcode_info.at(op).arg_types.at(arg_index);
}
const char* GetNameOf(Opcode op) {
std::string GetNameOf(Opcode op) {
if (OpcodeInfo::opcode_info.count(op) == 0)
return fmt::format("Unknown Opcode {}", static_cast<Opcode>(op));
return OpcodeInfo::opcode_info.at(op).name;
}
const char* GetNameOf(Type type) {
static const std::array<const char*, 14> names = {
"Void", "A32Reg", "A32ExtReg", "A64Reg", "A64Vec", "Opaque", "U1", "U8", "U16", "U32", "U64", "F32", "F64", "CoprocInfo"
std::string GetNameOf(Type type) {
static const std::array<const char*, 16> names = {
"Void", "A32Reg", "A32ExtReg", "A64Reg", "A64Vec", "Opaque", "U1", "U8", "U16", "U32", "U64", "F32", "F64", "CoprocInfo", "NZCVFlags", "Cond"
};
return names.at(static_cast<size_t>(type));
const size_t index = static_cast<size_t>(type);
if (index > names.size())
return fmt::format("Unknown Type {}", index);
return names.at(index);
}
bool AreTypesCompatible(Type t1, Type t2) {
return t1 == t2 || t1 == Type::Opaque || t2 == Type::Opaque;
}
std::ostream& operator<<(std::ostream& o, Opcode opcode) {
return o << GetNameOf(opcode);
}
std::ostream& operator<<(std::ostream& o, Type type) {
return o << GetNameOf(type);
}
} // namespace Dynarmic::IR

10
src/frontend/ir/opcodes.h
View file

@ -6,6 +6,9 @@
#pragma once
#include <iosfwd>
#include <string>
#include "common/common_types.h"
namespace Dynarmic::IR {
@ -66,12 +69,15 @@ size_t GetNumArgsOf(Opcode op);
Type GetArgTypeOf(Opcode op, size_t arg_index);
/// Get the name of an opcode.
const char* GetNameOf(Opcode op);
std::string GetNameOf(Opcode op);
/// Get the name of a type.
const char* GetNameOf(Type type);
std::string GetNameOf(Type type);
/// @returns true if t1 and t2 are compatible types
bool AreTypesCompatible(Type t1, Type t2);
std::ostream& operator<<(std::ostream& o, Opcode opcode);
std::ostream& operator<<(std::ostream& o, Type type);
} // namespace Dynarmic::IR

8
tests/A32/skyeye_interpreter/dyncom/arm_dyncom_interpreter.cpp
View file

@ -822,8 +822,8 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
// std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
// LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
// LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
ASSERT_MSG(false, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, "", inst);
ASSERT_MSG(false, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
ASSERT_MSG(false, "Decode failure.\tPC : [0x{:x}]\tInstruction : {} [{:x}]", phys_addr, "", inst);
ASSERT_MSG(false, "cpsr=0x{:x}, cpu->TFlag={}, r15=0x{:x}", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
CITRA_IGNORE_EXIT(-1);
}
inst_base = arm_instruction_trans[idx](inst, idx);
@ -1960,7 +1960,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
// LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
// inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
ASSERT_MSG(false, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
ASSERT_MSG(false, "MCRR executed | Coprocessor: {}, CRm {}, opc1: {}, Rt: {}, Rt2: {}",
inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
}
@ -2048,7 +2048,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
// LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
// inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
ASSERT_MSG(false, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
ASSERT_MSG(false, "MRRC executed | Coprocessor: {}, CRm {}, opc1: {}, Rt: {}, Rt2: {}",
inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
}

2
tests/A32/skyeye_interpreter/skyeye_common/armstate.cpp
View file

@ -469,7 +469,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
}
// LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
ASSERT_MSG(false, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
ASSERT_MSG(false, "MRC CRn={}, CRm={}, OP1={} OP2={} is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
return 0;
}

2
tests/A32/skyeye_interpreter/skyeye_common/vfp/vfp.cpp
View file

@ -161,7 +161,7 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
if (exceptions == VFP_EXCEPTION_ERROR) {
// LOG_CRITICAL(Core_ARM11, "unhandled bounce %x", inst);
// Crash();
ASSERT_MSG(false, "unhandled bounce %x", inst);
ASSERT_MSG(false, "unhandled bounce {:08x}", inst);
}
/*

2
tests/A32/skyeye_interpreter/skyeye_common/vfp/vfpsingle.cpp
View file

@ -1295,7 +1295,7 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
if (!fop->fn) {
// LOG_CRITICAL(Core_ARM11, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst), inst, state->Reg[15]);
// Crash();
ASSERT_MSG(false, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst), inst, state->Reg[15]);
ASSERT_MSG(false, "could not find single op {}, inst=0x{:08x}@0x{:08x}", FEXT_TO_IDX(inst), inst, state->Reg[15]);
goto invalid;
}

8
tests/A32/testenv.h
View file

@ -7,7 +7,7 @@
#pragma once
#include <array>
#include <cinttypes>
#include <cstring>
#include <map>
#include <dynarmic/A32/a32.h>
@ -71,11 +71,11 @@ public:
MemoryWrite32(vaddr + 4, static_cast<u32>(value >> 32));
}
void InterpreterFallback(u32 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback(%08x, %zu)", pc, num_instructions); }
void InterpreterFallback(u32 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:08x}, {})", pc, num_instructions); }
void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC(%u)", swi); }
void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override { ASSERT_MSG(false, "ExceptionRaised(%08x)", pc); }
void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override { ASSERT_MSG(false, "ExceptionRaised({:08x})", pc); }
void AddTicks(std::uint64_t ticks) override {
if (ticks > ticks_left) {

7
tests/A64/testenv.h
View file

@ -7,7 +7,6 @@
#pragma once
#include <array>
#include <cinttypes>
#include <map>
#include <dynarmic/A64/a64.h>
@ -77,11 +76,11 @@ public:
MemoryWrite64(vaddr + 8, value[1]);
}
void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback(%" PRIx64 ", %zu)", pc, num_instructions); }
void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC(%u)", swi); }
void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override { ASSERT_MSG(false, "ExceptionRaised(%" PRIx64 ")", pc); }
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override { ASSERT_MSG(false, "ExceptionRaised({:016x})", pc); }
void AddTicks(std::uint64_t ticks) override {
if (ticks > ticks_left) {

4
tests/A64/unicorn_emu/unicorn.cpp
View file

@ -10,7 +10,7 @@
#define CHECKED(expr) \
do { \
if (auto cerr_ = (expr)) { \
ASSERT_MSG(false, "Call " #expr " failed with error: %u (%s)\n", cerr_, \
ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \
uc_strerror(cerr_)); \
} \
} while (0)
@ -164,7 +164,7 @@ void Unicorn::InterruptHook(uc_engine* uc, u32 int_number, void* user_data) {
this_->testenv.CallSVC(iss);
break;
default:
ASSERT_MSG(false, "Unhandled interrupt: int_number: %#x, esr: %#x (ec: %#x, iss: %#x)", int_number, esr, ec, iss);
ASSERT_MSG(false, "Unhandled interrupt: int_number: {:#x}, esr: {:#x} (ec: {:#x}, iss: {:#x})", int_number, esr, ec, iss);
}
}

2
tests/CMakeLists.txt
View file

@ -47,7 +47,7 @@ endif()
include(CreateDirectoryGroups)
create_target_directory_groups(dynarmic_tests)
target_link_libraries(dynarmic_tests PRIVATE dynarmic boost catch)
target_link_libraries(dynarmic_tests PRIVATE dynarmic boost catch fmt)
target_include_directories(dynarmic_tests PRIVATE . ../src)
target_compile_options(dynarmic_tests PRIVATE ${DYNARMIC_CXX_FLAGS})