microinstruction: bug: Add missing opcodes
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@ -113,6 +113,8 @@ bool Inst::ReadsFromCPSR() const {
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case Opcode::A32GetCFlag:
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case Opcode::A32GetVFlag:
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case Opcode::A32GetGEFlags:
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case Opcode::ConditionalSelect32:
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case Opcode::ConditionalSelect64:
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return true;
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default:
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@ -147,6 +149,8 @@ bool Inst::ReadsFromCoreRegister() const {
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case Opcode::A32GetExtendedRegister64:
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case Opcode::A64GetW:
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case Opcode::A64GetX:
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case Opcode::A64GetD:
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case Opcode::A64GetQ:
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case Opcode::A64GetSP:
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return true;
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@ -163,6 +167,8 @@ bool Inst::WritesToCoreRegister() const {
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case Opcode::A32BXWritePC:
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case Opcode::A64SetW:
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case Opcode::A64SetX:
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case Opcode::A64SetD:
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case Opcode::A64SetQ:
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case Opcode::A64SetSP:
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case Opcode::A64SetPC:
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return true;
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