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IR: Implement FPVectorSub

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This commit is contained in:
MerryMage 2018-02-11 12:17:53 +00:00
parent 851fc83445
commit b9cd345ddc
5 changed files with 54 additions and 0 deletions
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1
src/CMakeLists.txt
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@ -167,6 +167,7 @@ if (ARCHITECTURE_x86_64)
backend_x64/emit_x64_packed.cpp
backend_x64/emit_x64_saturation.cpp
backend_x64/emit_x64_vector.cpp
backend_x64/emit_x64_vector_floating_point.cpp
backend_x64/hostloc.cpp
backend_x64/hostloc.h
backend_x64/jitstate_info.h

36
src/backend_x64/emit_x64_vector_floating_point.cpp Normal file
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@ -0,0 +1,36 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2016 MerryMage
* This software may be used and distributed according to the terms of the GNU
* General Public License version 2 or any later version.
*/
#include "backend_x64/block_of_code.h"
#include "backend_x64/emit_x64.h"
#include "frontend/ir/basic_block.h"
#include "frontend/ir/microinstruction.h"
namespace Dynarmic::BackendX64 {
using namespace Xbyak::util;
template <typename Function>
static void EmitVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(args[0]);
Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(args[1]);
(code.*fn)(xmm_a, xmm_b);
ctx.reg_alloc.DefineValue(inst, xmm_a);
}
void EmitX64::EmitFPVectorSub32(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::subps);
}
void EmitX64::EmitFPVectorSub64(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::subpd);
}
} // namespace Dynarmic::BackendX64

11
src/frontend/ir/ir_emitter.cpp
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@ -1139,6 +1139,17 @@ U64 IREmitter::FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_con
return Inst<U64>(Opcode::FPU32ToDouble, a, Imm1(round_to_nearest));
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorSub32, a, b);
case 64:
return Inst<U128>(Opcode::FPVectorSub64, a, b);
}
UNREACHABLE();
return {};
}
void IREmitter::Breakpoint() {
Inst(Opcode::Breakpoint);
}

2
src/frontend/ir/ir_emitter.h
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@ -247,6 +247,8 @@ public:
U64 FPS32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U64 FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
void Breakpoint();
void SetTerm(const Terminal& terminal);

4
src/frontend/ir/opcodes.inc
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@ -289,6 +289,10 @@ OPCODE(FPS32ToSingle, T::U32, T::U32, T::U1
OPCODE(FPU32ToDouble, T::U64, T::U32, T::U1 )
OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 )
// Floating-point vector instructions
OPCODE(FPVectorSub32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorSub64, T::U128, T::U128, T::U128 )
// A32 Memory access
A32OPC(ClearExclusive, T::Void, )
A32OPC(SetExclusive, T::Void, T::U32, T::U8 )