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A64: Implement SUB (vector)

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This commit is contained in:
MerryMage 2018-02-10 23:58:33 +00:00
parent bd106c3ae7
commit faeb77e8c4
2 changed files with 16 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -747,7 +747,7 @@ INST(ORN_asimd, "ORN (vector)", "0Q001
//INST(UMIN, "UMIN", "0Q101110zz1mmmmm011011nnnnnddddd")
//INST(UABD, "UABD", "0Q101110zz1mmmmm011101nnnnnddddd")
//INST(UABA, "UABA", "0Q101110zz1mmmmm011111nnnnnddddd")
//INST(SUB_2, "SUB (vector)", "0Q101110zz1mmmmm100001nnnnnddddd")
INST(SUB_2, "SUB (vector)", "0Q101110zz1mmmmm100001nnnnnddddd")
INST(CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd")
//INST(MLS_vec, "MLS (vector)", "0Q101110zz1mmmmm100101nnnnnddddd")
//INST(PMUL, "PMUL", "0Q101110zz1mmmmm100111nnnnnddddd")

15
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -98,6 +98,21 @@ bool TranslatorVisitor::ORN_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
auto operand1 = V(datasize, Vn);
auto operand2 = V(datasize, Vm);
auto result = ir.VectorSub(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::CMEQ_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();