suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

IR: Implement VectorZeroExtend

Browse source
This commit is contained in:
MerryMage 2018-02-10 10:28:38 +00:00
parent d3a4e1efe2
commit 59ace60b03
4 changed files with 61 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
src/backend_x64/emit_x64_vector.cpp
View file

@ -634,6 +634,47 @@ void EmitX64::EmitVectorLogicalShiftLeft64(EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, result);
}
static void EmitVectorZeroExtend(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int size) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Xmm zeros = ctx.reg_alloc.ScratchXmm();
code.pxor(zeros, zeros);
switch (size) {
case 8:
code.punpcklbw(a, zeros);
break;
case 16:
code.punpcklwd(a, zeros);
break;
case 32:
code.punpckldq(a, zeros);
break;
case 64:
code.punpcklqdq(a, zeros);
break;
}
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitVectorZeroExtend8(EmitContext& ctx, IR::Inst* inst) {
EmitVectorZeroExtend(code, ctx, inst, 8);
}
void EmitX64::EmitVectorZeroExtend16(EmitContext& ctx, IR::Inst* inst) {
EmitVectorZeroExtend(code, ctx, inst, 16);
}
void EmitX64::EmitVectorZeroExtend32(EmitContext& ctx, IR::Inst* inst) {
EmitVectorZeroExtend(code, ctx, inst, 32);
}
void EmitX64::EmitVectorZeroExtend64(EmitContext& ctx, IR::Inst* inst) {
EmitVectorZeroExtend(code, ctx, inst, 64);
}
void EmitX64::EmitVectorZeroUpper(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

15
src/frontend/ir/ir_emitter.cpp
View file

@ -919,6 +919,21 @@ U128 IREmitter::VectorPairedAdd(size_t esize, const U128& a, const U128& b) {
return {};
}
U128 IREmitter::VectorZeroExtend(size_t original_esize, const U128& a) {
switch (original_esize) {
case 8:
return Inst<U128>(Opcode::VectorZeroExtend8, a);
case 16:
return Inst<U128>(Opcode::VectorZeroExtend16, a);
case 32:
return Inst<U128>(Opcode::VectorZeroExtend32, a);
case 64:
return Inst<U128>(Opcode::VectorZeroExtend64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorZeroUpper(const U128& a) {
return Inst<U128>(Opcode::VectorZeroUpper, a);
}

1
src/frontend/ir/ir_emitter.h
View file

@ -219,6 +219,7 @@ public:
U128 VectorOr(const U128& a, const U128& b);
U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b);
U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b);
U128 VectorZeroExtend(size_t original_esize, const U128& a);
U128 VectorZeroUpper(const U128& a);
U32U64 FPAbs(const U32U64& a);

4
src/frontend/ir/opcodes.inc
View file

@ -233,6 +233,10 @@ OPCODE(VectorPairedAdd8, T::U128, T::U128, T::U128
OPCODE(VectorPairedAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
OPCODE(VectorZeroExtend8, T::U128, T::U128 )
OPCODE(VectorZeroExtend16, T::U128, T::U128 )
OPCODE(VectorZeroExtend32, T::U128, T::U128 )
OPCODE(VectorZeroExtend64, T::U128, T::U128 )
OPCODE(VectorZeroUpper, T::U128, T::U128 )
// Floating-point operations