MerryMage
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b93ae62acf
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thumb32: Add coprocessor instructions
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2021-05-13 18:15:35 +01:00 |
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MerryMage
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61333917a4
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thumb32: Implement MRS (register)
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2021-05-04 12:43:38 +01:00 |
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MerryMage
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a5a210a9a5
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T32: Add ASIMD instructions
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2021-05-04 00:09:55 +01:00 |
|
MerryMage
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d1e62b9993
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T32: Add VFP instructions
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2021-05-04 00:09:55 +01:00 |
|
MerryMage
|
e19f898aa2
|
ir: Reorganize to new top level folder
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2021-04-21 22:22:07 +01:00 |
|
Lioncash
|
f5263cc196
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thumb32: Implement exclusive loads
Implements the remaining loads for ARMv7
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2021-04-19 19:46:19 +01:00 |
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Lioncash
|
6241ff6be2
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thumb32: Implement STREX variants
Implements the exclusive store instructions. Now all that remains for
ARMv7 load/stores to be done is the exclusive loads.
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2021-04-10 17:15:19 +01:00 |
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MerryMage
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f77b0e2fbe
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A32/thumb16: Implement IT instruction
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2021-02-07 20:41:48 +00:00 |
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MerryMage
|
68bd9547c5
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fuzz_arm: Correctly print thumb instruction listing
|
2021-02-07 20:41:48 +00:00 |
|
MerryMage
|
a599c29d9e
|
testenv: Ignore warning C4309
|
2021-02-07 09:57:17 +00:00 |
|
MerryMage
|
b252636dc3
|
a32_unicorn: Halt when PC leaves code_mem
|
2021-02-06 22:15:02 +00:00 |
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MerryMage
|
331a02e02e
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fuzz_arm: Add fuzzing for thumb instructions
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2021-02-06 21:41:01 +00:00 |
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Lioncash
|
23619c8c6a
|
thumb32: Implement SHSUB8/UHSUB8
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2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
9d2570470e
|
thumb32: Implement SHADD8/UHADD8
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
afad76078d
|
thumb32: Implement SHSUB16/UHSUB16
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
51b7c32d02
|
thumb32: Implement SHSAX/UHSAX
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
f0a219fcd0
|
thumb32: Implement SHASX/UHASX
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
94f8efbb03
|
thumb32: Implement SHADD16/UHADD16
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
aa49b0db89
|
thumb32: Implement QSUB8/UQSUB8
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
874ab6a7b6
|
thumb32: Implement QADD8/UQADD8
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
d923fb24c6
|
thumb32: Implement QSUB16/UQSUB16
|
2021-02-01 17:50:46 -05:00 |
|
Lioncash
|
416fe26df0
|
thumb32: Implement QSAX/UQSAX
|
2021-02-01 17:50:14 -05:00 |
|
Lioncash
|
ad7c8bd042
|
thumb32: Implement QASX/UQASX
|
2021-02-01 17:31:30 -05:00 |
|
Lioncash
|
f52b8f924c
|
thumb32: Implement QADD16/UQADD16
|
2021-02-01 17:31:30 -05:00 |
|
Lioncash
|
6f593da41b
|
thumb32: Implement SSUB8/USUB8
|
2021-02-01 17:31:27 -05:00 |
|
Lioncash
|
271354ee95
|
thumb32: Implement SADD8/UADD8
|
2021-02-01 16:44:11 -05:00 |
|
Lioncash
|
8f42fd5c0e
|
thumb32: Implement SSUB16/USUB16
|
2021-02-01 16:41:02 -05:00 |
|
Lioncash
|
0e28c63456
|
thumb32: Implement SSAX/USAX
|
2021-02-01 16:36:18 -05:00 |
|
Lioncash
|
21e404d3ab
|
thumb32: Implement SASX/UASX
|
2021-02-01 16:31:25 -05:00 |
|
Lioncash
|
d529417875
|
thumb32: Implement SADD16/UADD16
|
2021-02-01 16:19:33 -05:00 |
|
Lioncash
|
36fc596a51
|
thumb32: Implement QADD
|
2021-02-01 15:44:09 -05:00 |
|
Lioncash
|
cd6e4c7afd
|
thumb32: Implement QSUB
|
2021-02-01 15:42:14 -05:00 |
|
Lioncash
|
65365ad2a3
|
thumb32: Implement QDADD
|
2021-02-01 15:39:39 -05:00 |
|
Lioncash
|
c60cf921ee
|
thumb32: Implement REV
|
2021-02-01 15:30:40 -05:00 |
|
Lioncash
|
0304dc7ce4
|
thumb32: Implement REV16
|
2021-02-01 15:27:31 -05:00 |
|
Lioncash
|
cee31c5274
|
thumb32: Implement RBIT
|
2021-02-01 15:20:24 -05:00 |
|
Lioncash
|
e2bc7eeb93
|
thumb32: Implement REVSH
|
2021-02-01 15:16:53 -05:00 |
|
Lioncash
|
95dabcf48e
|
fuzz_thumb: Allow running only Thumb-16 tests
|
2021-02-01 15:04:29 -05:00 |
|
Lioncash
|
1ad99bb9b5
|
thumb32: Implement SEL
|
2021-02-01 15:01:21 -05:00 |
|
Lioncash
|
8d53048750
|
thumb32: Implement CLZ
Also fleshes out the generator to allow for generating thumb32
instructions as well.
|
2021-02-01 14:54:04 -05:00 |
|
MerryMage
|
4ba1f8b9e7
|
Add optimization flags to disable specific optimizations
|
2020-07-04 11:04:10 +01:00 |
|
MerryMage
|
3eed024caf
|
asimd_three_same: Ignore Q=1 for VPADD (floating-point)
|
2020-07-04 11:04:10 +01:00 |
|
MerryMage
|
2008fda88b
|
emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed
|
2020-06-22 22:54:38 +01:00 |
|
MerryMage
|
3ea49fc6d6
|
A32: Implement VFPv3 VCT (between floating-point and fixed-point)
|
2020-06-22 22:08:58 +01:00 |
|
MerryMage
|
69a1d58a2b
|
A32: Implement ASIMD VMULL
|
2020-06-21 10:00:24 +01:00 |
|
MerryMage
|
70d071e6ab
|
fuzz_arm: Test large random blocks
|
2020-06-21 00:41:54 +01:00 |
|
MerryMage
|
214c1d6002
|
fuzz_arm: Test testable parts of ASIMD VRECPE and VRSQRTE
|
2020-06-20 15:17:39 +01:00 |
|
MerryMage
|
92cb4a5a34
|
A32: Implement ASIMD VRSQRTE
|
2020-06-20 15:13:22 +01:00 |
|
MerryMage
|
8912496206
|
fuzz_arm: Unicorn has incorrect VRSQRTS implementation
|
2020-06-20 15:07:50 +01:00 |
|
MerryMage
|
6f59c2cd8e
|
A32: Implement ASIMD VRECPE
|
2020-06-20 15:07:06 +01:00 |
|