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Author SHA1 Message Date
MerryMage
c6ecc835b6 ASIMD: Implement VCVT (between half-precision and single-precision) 2021-05-16 23:48:29 +01:00
MerryMage
d93145bd04 decoder_tests: Only run ASIMD decoder test explicitly 
The test is a 2 minute test whose result only really matters if the ASIMD decoder is modified.
 2021-05-16 21:48:25 +01:00
MerryMage
9de58f2875 assert: Check for unreachable code if DYNARMIC_IGNORE_ASSERTS isn't enabled 2021-05-16 21:46:44 +01:00
MerryMage
5bf74b5f04 reg_alloc: Determine size of spill slot with sizeof 2021-05-16 21:46:10 +01:00
MerryMage
b6bff56523 translate_thumb: Update current_instruction_size in TranslateSingleThumbInstruction 2021-05-16 10:31:30 +01:00
Wunkolo
2c0be5e18c emit_x64_vector: AVX512 Implementation of EmitVectorNarrow{32,64} 
Includes a new test case with the XTN instruction to verify
the implementation
 2021-05-16 10:02:49 +01:00
MerryMage
1643e8f3c6 translate_thumb: VFP/ASIMD conflict with coprocessor instructions 2021-05-15 20:54:35 +01:00
Wunkolo
105b464bc1 backend/x64: Implement HostFeature 2021-05-14 21:20:21 +01:00
MerryMage
b93ae62acf thumb32: Add coprocessor instructions 2021-05-13 18:15:35 +01:00
MerryMage
5ebe11c329 reg_alloc: Inform RegAlloc about rsp changes 2021-05-07 12:47:55 +01:00
MerryMage
05a6b5f623 translate_thumb: Permit ASIMD element or structure load/store instructions to be translated 2021-05-07 12:47:55 +01:00
MerryMage
62ecc2537e print_info: Add thumb mode 2021-05-07 08:24:51 +01:00
sunho
cb79bfa1dc thumb32: Support setflags in shift reg instructions 2021-05-05 11:47:49 +01:00
MerryMage
075fdeaee0 thumb32: Add Rn argument to ADD/SUB (Plain Binary Immediate) 2021-05-05 11:47:49 +01:00
MerryMage
ebe44dab7a stack_layout: Ignore warning C4324 for StackLayout 
We expect the structure to be padded
 2021-05-04 16:26:28 +01:00
MerryMage
462c884685 frontend/A32: Correct more IT state 2021-05-04 16:25:24 +01:00
MerryMage
c5f5c1d40f frontend: Standardize emitted IR for exception raising 2021-05-04 16:14:26 +01:00
MerryMage
3b2c6afdc2 backend/x64: Move cycles_remaining and cycles_to_run from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
d6592c7142 Remove ExceptionalExit hack 2021-05-04 14:40:13 +01:00
MerryMage
030ff82ba8 backend/x64: Move check_bit from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
a1950d1d2f backend/x64: Move save_host_MXCSR from JitState to stack 2021-05-04 14:19:05 +01:00
MerryMage
ddbc50cee0 backend/x64: Move spill from JitState onto the stack 2021-05-04 14:18:44 +01:00
MerryMage
f8d8ea0deb thumb32: Implement MRS (register) 2021-05-04 12:43:51 +01:00
MerryMage
61333917a4 thumb32: Implement MRS (register) 2021-05-04 12:43:38 +01:00
MerryMage
a5a210a9a5 T32: Add ASIMD instructions 2021-05-04 00:09:55 +01:00
MerryMage
d1e62b9993 T32: Add VFP instructions 2021-05-04 00:09:55 +01:00
MerryMage
cd837c5b37 A32: Merge ArmTranslateVistor and ThumbTranslateVisitor 2021-05-04 00:09:55 +01:00
MerryMage
6d292e3eac decoder: Ensure more compiler-time computation 
Replace with consteval when C++20 hits
 2021-05-03 13:09:51 +01:00
MerryMage
795b9bea9a Remove ChangeProcessorID hack 
* No library users require this hack any longer.
 2021-05-01 20:33:14 +01:00
MerryMage
6404f58d23 rsqrt_test: Fix on GCC 2021-05-01 20:33:14 +01:00
MerryMage
6759942b56 emit_x64_data_processing: Correct bug in ArithmeticShiftRight64 
This branch of this implementation is unused, and thus has not been tested.
 2021-04-27 18:51:23 +01:00
MerryMage
68088c277c emit_x64_data_processing: Reduce codesize of RotateRight32 for carry case 2021-04-26 21:57:22 +01:00
MerryMage
f77b98de36 emit_x64_data_processing: Reduce codesize of ArithmeticShiftRight32 for carry case 2021-04-26 21:57:08 +01:00
MerryMage
a2a687f208 emit_x64_data_processing: Reduce codesize of LogicalShiftRight32 for carry case 2021-04-26 21:56:42 +01:00
MerryMage
58ff457339 emit_x64_data_processing: Reduce codesize of LogicalShiftLeft32 for carry case 2021-04-26 21:35:06 +01:00
MerryMage
510862e50c backend/x64: Change V flag testing to cmp instead of add 
Prefer a non-destructive read to a destructive read.
 2021-04-26 00:26:28 +01:00
MerryMage
f35d98c923 fuzz_with_unicorn: Widen scope of floating point fuzzing 2021-04-26 00:26:28 +01:00
MerryMage
3f74a839b9 emit_x64_floating_point: Optimize 64-bit EmitFPRSqrtEstimate 2021-04-26 00:26:28 +01:00
MerryMage
7bc9e36ed7 emit_x64_floating_point: Optimize 32-bit EmitFPRSqrtEstimate 2021-04-26 00:26:28 +01:00
MerryMage
e19f898aa2 ir: Reorganize to new top level folder 2021-04-21 22:22:07 +01:00
MerryMage
5bec200c36 block_of_code: Add santiy check that far_code_offset < total_code_size 2021-04-21 18:26:26 +01:00
MerryMage
08ed8b4a11 abi: Consolodate ABI information into one place 2021-04-21 18:25:04 +01:00
Lioncash
f5263cc196 thumb32: Implement exclusive loads 
Implements the remaining loads for ARMv7
 2021-04-19 19:46:19 +01:00
MerryMage
9c6332fcbd thumb32_load_store_dual: imm8 in STREX should be shifted left by 2 2021-04-19 18:57:28 +01:00
MerryMage
b2a4da5e65 block_of_code: Correct SpaceRemaining 2021-04-11 15:37:25 +01:00
Lioncash
6241ff6be2 thumb32: Implement STREX variants 
Implements the exclusive store instructions. Now all that remains for
ARMv7 load/stores to be done is the exclusive loads.
 2021-04-10 17:15:19 +01:00
MerryMage
d8066b091b decoder/arm: Complete instruction version information 2021-04-10 17:11:24 +01:00
merry
71491c0a4a
Merge pull request #596 from degasus/fix_perf_register 
backend/x64: Fix PerfMapRegister usages.
 2021-04-05 21:43:10 +01:00
MerryMage
9ab83180db {a32,a64}_interface: Clear exclusive state during an exceptional exit 
This is normally done by the ERET instruction during a service call.
 2021-04-02 19:33:28 +01:00
MerryMage
c788bcdf17 block_of_code: Enable configuration of code cache sizes 2021-04-02 11:17:46 +01:00