thumb32: Implement SHADD16/UHADD16
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aa49b0db89
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94f8efbb03
4 changed files with 35 additions and 2 deletions
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@ -247,7 +247,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_QSUB16, "QSUB16", "111110101101nnnn1111dddd0001mmmm"),
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INST(&V::thumb32_QADD8, "QADD8", "111110101000nnnn1111dddd0001mmmm"),
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INST(&V::thumb32_QSUB8, "QSUB8", "111110101100nnnn1111dddd0001mmmm"),
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//INST(&V::thumb32_SHADD16, "SHADD16", "111110101001----1111----0010----"),
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INST(&V::thumb32_SHADD16, "SHADD16", "111110101001nnnn1111dddd0010mmmm"),
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//INST(&V::thumb32_SHASX, "SHASX", "111110101010----1111----0010----"),
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//INST(&V::thumb32_SHSAX, "SHSAX", "111110101110----1111----0010----"),
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//INST(&V::thumb32_SHSUB16, "SHSUB16", "111110101101----1111----0010----"),
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@ -267,7 +267,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_UQSUB16, "UQSUB16", "111110101101nnnn1111dddd0101mmmm"),
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INST(&V::thumb32_UQADD8, "UQADD8", "111110101000nnnn1111dddd0101mmmm"),
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INST(&V::thumb32_UQSUB8, "UQSUB8", "111110101100nnnn1111dddd0101mmmm"),
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//INST(&V::thumb32_UHADD16, "UHADD16", "111110101001----1111----0110----"),
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INST(&V::thumb32_UHADD16, "UHADD16", "111110101001nnnn1111dddd0110mmmm"),
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//INST(&V::thumb32_UHASX, "UHASX", "111110101010----1111----0110----"),
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//INST(&V::thumb32_UHSAX, "UHSAX", "111110101110----1111----0110----"),
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//INST(&V::thumb32_UHSUB16, "UHSUB16", "111110101101----1111----0110----"),
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@ -362,4 +362,30 @@ bool ThumbTranslatorVisitor::thumb32_UQSUB16(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SHADD16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedHalvingAddS16(reg_n, reg_m);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UHADD16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedHalvingAddU16(reg_n, reg_m);
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ir.SetRegister(d, result);
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return true;
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}
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} // namespace Dynarmic::A32
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@ -154,6 +154,9 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_UQSAX(Reg n, Reg d, Reg m);
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bool thumb32_UQSUB8(Reg n, Reg d, Reg m);
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bool thumb32_UQSUB16(Reg n, Reg d, Reg m);
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bool thumb32_SHADD16(Reg n, Reg d, Reg m);
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bool thumb32_UHADD16(Reg n, Reg d, Reg m);
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};
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} // namespace Dynarmic::A32
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@ -432,6 +432,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
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three_reg_not_r15),
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ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
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three_reg_not_r15),
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ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
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@ -444,6 +446,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16
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