thumb32: Implement SHADD8/UHADD8
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afad76078d
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9d2570470e
4 changed files with 34 additions and 2 deletions
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@ -251,7 +251,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_SHASX, "SHASX", "111110101010nnnn1111dddd0010mmmm"),
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INST(&V::thumb32_SHSAX, "SHSAX", "111110101110nnnn1111dddd0010mmmm"),
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INST(&V::thumb32_SHSUB16, "SHSUB16", "111110101101nnnn1111dddd0010mmmm"),
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//INST(&V::thumb32_SHADD8, "SHADD8", "111110101000----1111----0010----"),
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INST(&V::thumb32_SHADD8, "SHADD8", "111110101000nnnn1111dddd0010mmmm"),
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//INST(&V::thumb32_SHSUB8, "SHSUB8", "111110101100----1111----0010----"),
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// Parallel Addition and Subtraction (unsigned)
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@ -271,7 +271,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_UHASX, "UHASX", "111110101010nnnn1111dddd0110mmmm"),
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INST(&V::thumb32_UHSAX, "UHSAX", "111110101110nnnn1111dddd0110mmmm"),
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INST(&V::thumb32_UHSUB16, "UHSUB16", "111110101101nnnn1111dddd0110mmmm"),
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//INST(&V::thumb32_UHADD8, "UHADD8", "111110101000----1111----0110----"),
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INST(&V::thumb32_UHADD8, "UHADD8", "111110101000nnnn1111dddd0110mmmm"),
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//INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100----1111----0110----"),
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// Miscellaneous Operations
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@ -362,6 +362,19 @@ bool ThumbTranslatorVisitor::thumb32_UQSUB16(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SHADD8(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedHalvingAddS8(reg_n, reg_m);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SHADD16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@ -414,6 +427,19 @@ bool ThumbTranslatorVisitor::thumb32_SHSUB16(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UHADD8(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedHalvingAddU8(reg_n, reg_m);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UHADD16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@ -155,10 +155,12 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_UQSUB8(Reg n, Reg d, Reg m);
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bool thumb32_UQSUB16(Reg n, Reg d, Reg m);
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bool thumb32_SHADD8(Reg n, Reg d, Reg m);
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bool thumb32_SHADD16(Reg n, Reg d, Reg m);
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bool thumb32_SHASX(Reg n, Reg d, Reg m);
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bool thumb32_SHSAX(Reg n, Reg d, Reg m);
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bool thumb32_SHSUB16(Reg n, Reg d, Reg m);
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bool thumb32_UHADD8(Reg n, Reg d, Reg m);
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bool thumb32_UHADD16(Reg n, Reg d, Reg m);
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bool thumb32_UHASX(Reg n, Reg d, Reg m);
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bool thumb32_UHSAX(Reg n, Reg d, Reg m);
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@ -432,6 +432,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX
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@ -452,6 +454,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX
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