thumb32: Implement SSAX/USAX
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21e404d3ab
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0e28c63456
4 changed files with 36 additions and 2 deletions
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@ -237,7 +237,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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// Parallel Addition and Subtraction (signed)
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INST(&V::thumb32_SADD16, "SADD16", "111110101001nnnn1111dddd0000mmmm"),
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INST(&V::thumb32_SASX, "SASX", "111110101010nnnn1111dddd0000mmmm"),
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//INST(&V::thumb32_SSAX, "SSAX", "111110101110----1111----0000----"),
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INST(&V::thumb32_SSAX, "SSAX", "111110101110nnnn1111dddd0000mmmm"),
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//INST(&V::thumb32_SSUB16, "SSUB16", "111110101101----1111----0000----"),
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//INST(&V::thumb32_SADD8, "SADD8", "111110101000----1111----0000----"),
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//INST(&V::thumb32_SSUB8, "SSUB8", "111110101100----1111----0000----"),
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@ -257,7 +257,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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// Parallel Addition and Subtraction (unsigned)
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INST(&V::thumb32_UADD16, "UADD16", "111110101001nnnn1111dddd0100mmmm"),
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INST(&V::thumb32_UASX, "UASX", "111110101010nnnn1111dddd0100mmmm"),
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//INST(&V::thumb32_USAX, "USAX", "111110101110----1111----0100----"),
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INST(&V::thumb32_USAX, "USAX", "111110101110nnnn1111dddd0100mmmm"),
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//INST(&V::thumb32_USUB16, "USUB16", "111110101101----1111----0100----"),
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//INST(&V::thumb32_UADD8, "UADD8", "111110101000----1111----0100----"),
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//INST(&V::thumb32_USUB8, "USUB8", "111110101100----1111----0100----"),
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@ -35,6 +35,20 @@ bool ThumbTranslatorVisitor::thumb32_SASX(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SSAX(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedSubAddS16(reg_n, reg_m);
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ir.SetRegister(d, result.result);
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ir.SetGEFlags(result.ge);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UADD16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@ -63,4 +77,18 @@ bool ThumbTranslatorVisitor::thumb32_UASX(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_USAX(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedSubAddU16(reg_n, reg_m);
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ir.SetRegister(d, result.result);
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ir.SetGEFlags(result.ge);
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return true;
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}
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} // namespace Dynarmic::A32
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@ -131,8 +131,10 @@ struct ThumbTranslatorVisitor final {
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// thumb32 parallel add/sub instructions
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bool thumb32_SADD16(Reg n, Reg d, Reg m);
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bool thumb32_SASX(Reg n, Reg d, Reg m);
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bool thumb32_SSAX(Reg n, Reg d, Reg m);
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bool thumb32_UADD16(Reg n, Reg d, Reg m);
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bool thumb32_UASX(Reg n, Reg d, Reg m);
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bool thumb32_USAX(Reg n, Reg d, Reg m);
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};
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} // namespace Dynarmic::A32
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@ -418,10 +418,14 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
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three_reg_not_r15),
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ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
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three_reg_not_r15),
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ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
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three_reg_not_r15),
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};
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const auto instruction_select = [&]() -> u32 {
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