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A32: Implement ASIMD VMULL

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This commit is contained in:
MerryMage 2020-06-21 10:00:24 +01:00
parent 8c23f02330
commit 69a1d58a2b
4 changed files with 26 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
View file

@ -30,7 +30,7 @@ INST(asimd_VCEQ_reg, "VCEG (register)", "111100110Dzznnnndddd100
INST(asimd_VMLA, "VMLA/VMLS", "1111001o0Dzznnnndddd1001NQM0mmmm") // ASIMD
//INST(asimd_VMLAL, "VMLAL/VMLSL", "1111001U1Dzznnnndddd10o0N0M0mmmm") // ASIMD
INST(asimd_VMUL, "VMUL", "1111001P0Dzznnnndddd1001NQM1mmmm") // ASIMD
//INST(asimd_VMULL, "VMULL", "1111001U1Dzznnnndddd11o0N0M0mmmm") // ASIMD
INST(asimd_VMULL, "VMULL", "1111001U1Dzznnnndddd11P0N0M0mmmm") // ASIMD
//INST(asimd_VPMAX, "VPMAX/VPMIN", "1111001U0-CC--------1010---B----") // ASIMD
//INST(asimd_VQDMULH, "VQDMULH", "111100100-CC--------1011---0----") // ASIMD
//INST(asimd_VQRDMULH, "VQRDMULH", "111100110-CC--------1011---0----") // ASIMD

23
src/frontend/A32/translate/impl/asimd_three_same.cpp
View file

@ -550,6 +550,29 @@ bool ArmTranslatorVisitor::asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size
return true;
}
bool ArmTranslatorVisitor::asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool P, bool N, bool M, size_t Vm) {
if (sz == 0b11 || (P & (U || sz == 0b10)) || Common::Bit<0>(Vd)) {
return UndefinedInstruction();
}
const size_t esize = P ? (sz == 0b00 ? 8 : 64) : 8U << sz;
const auto d = ToVector(true, Vd, D);
const auto m = ToVector(false, Vm, M);
const auto n = ToVector(false, Vn, N);
const auto extend_reg = [&](const auto& reg) {
return U ? ir.VectorZeroExtend(esize, reg) : ir.VectorSignExtend(esize, reg);
};
const auto reg_n = ir.GetVector(n);
const auto reg_m = ir.GetVector(m);
const auto result = P ? ir.VectorPolynomialMultiplyLong(esize, reg_m, reg_n)
: ir.VectorMultiply(2 * esize, extend_reg(reg_m), extend_reg(reg_n));
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VPADD(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q || sz == 0b11) {
return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -476,6 +476,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VCEQ_reg(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool P, bool N, bool M, size_t Vm);
bool asimd_VPADD(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VADD_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VSUB_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);

1
tests/A32/fuzz_arm.cpp
View file

@ -64,6 +64,7 @@ bool ShouldTestInst(u32 instruction, u32 pc, bool is_last_inst) {
// Currently unimplemented in Unicorn
case IR::Opcode::FPVectorRecipEstimate16:
case IR::Opcode::FPVectorRSqrtEstimate16:
case IR::Opcode::VectorPolynomialMultiplyLong64:
return false;
default:
continue;