MerryMage
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90a053a5e4
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emit_x64_vector: Order alphabetically
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e7041d7196
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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a455ff70c9
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decoder/a64: Don't rearrange unrelated decoders
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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faeb77e8c4
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A64: Implement SUB (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bd106c3ae7
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A64: Implement SIMD instruction SSRA, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f58aba9871
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A64: Implement SIMD instruction SSHR, vector variant
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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653c82d8f0
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impl: Improve Vpart setter
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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e858ce0b35
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A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1423584f9f
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constant_pool: Allow for 128-bit constants
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
69de50a878
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
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cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
3f93c77ace
|
A64: Implement SIMD instruction USRA, vector variant
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
fb9d20f27f
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A64: Implement SIMD instruction USHR, vector variant
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7ff280827b
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A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
f6247125c0
|
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d74f4e35f6
|
block_of_code: Increase constant pool size
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
e69288f803
|
devirtualize: MinGW uses Intanium MFP ABI
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ad428cbd7a
|
callback: Properly handle calls with return pointers and simplify interface
|
2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
15871910af
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Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7a87e3fc55
|
devirtualize: Handle Windows ABI
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
12173a8792
|
travis: Switch to yuzu-emu's unicorn repository
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
a78e13ff19
|
fuzz_arm: Use SCOPE_FAIL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ba4a779c62
|
A32/decoder/arm: bug: Correct bitstring for SRS
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
f808a0fbde
|
devirtualize: Devirtualize Itanium ABI MFPs at runtime
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
afe16fa0f3
|
cast_util: Add BitCast and BitCastPointee
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
4e33629b0e
|
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
35a29a9665
|
A64: Implement ZIP1
|
2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
586854117b
|
Implemented UMULH and SMULH instructions
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1a7b7b541a
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8ab7d8175c
|
impl: Add AdvSIMDExpandImm
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ea69cb4474
|
A64: Implement SUB (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
|
A64: Implement ADD (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2a0850c068
|
A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7b33772ac6
|
A64: Implement BIC (vector, register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ca43be4146
|
docs: Update documentation (2018-02-05)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
eb5591859c
|
A64: Implement FMOV (general)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
dd88cee15a
|
translate/impl: Add Vpart
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
cc9efd13c9
|
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
81713c2b77
|
A64: Implement FCCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
44c3c2312a
|
a64_jitstate: Remove unnecessary FPSCR_nzcv member
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
aac5af50e2
|
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
2ee39d6b36
|
A64: Implement FMOV (register)
|
2020-04-22 20:46:13 +01:00 |
|