MerryMage
6d0a049fb2
A32/decode: Split thumb16
2021-02-06 21:25:24 +00:00
MerryMage
ac9e1ccb1c
A32/thumb16: Fix bug in CBZ/CBNZ
2021-02-06 21:25:24 +00:00
Lioncash
23619c8c6a
thumb32: Implement SHSUB8/UHSUB8
2021-02-01 17:50:46 -05:00
Lioncash
9d2570470e
thumb32: Implement SHADD8/UHADD8
2021-02-01 17:50:46 -05:00
Lioncash
afad76078d
thumb32: Implement SHSUB16/UHSUB16
2021-02-01 17:50:46 -05:00
Lioncash
51b7c32d02
thumb32: Implement SHSAX/UHSAX
2021-02-01 17:50:46 -05:00
Lioncash
f0a219fcd0
thumb32: Implement SHASX/UHASX
2021-02-01 17:50:46 -05:00
Lioncash
94f8efbb03
thumb32: Implement SHADD16/UHADD16
2021-02-01 17:50:46 -05:00
Lioncash
aa49b0db89
thumb32: Implement QSUB8/UQSUB8
2021-02-01 17:50:46 -05:00
Lioncash
874ab6a7b6
thumb32: Implement QADD8/UQADD8
2021-02-01 17:50:46 -05:00
Lioncash
d923fb24c6
thumb32: Implement QSUB16/UQSUB16
2021-02-01 17:50:46 -05:00
Lioncash
416fe26df0
thumb32: Implement QSAX/UQSAX
2021-02-01 17:50:14 -05:00
Lioncash
ad7c8bd042
thumb32: Implement QASX/UQASX
2021-02-01 17:31:30 -05:00
Lioncash
f52b8f924c
thumb32: Implement QADD16/UQADD16
2021-02-01 17:31:30 -05:00
Lioncash
6f593da41b
thumb32: Implement SSUB8/USUB8
2021-02-01 17:31:27 -05:00
Lioncash
271354ee95
thumb32: Implement SADD8/UADD8
2021-02-01 16:44:11 -05:00
Lioncash
8f42fd5c0e
thumb32: Implement SSUB16/USUB16
2021-02-01 16:41:02 -05:00
Lioncash
0e28c63456
thumb32: Implement SSAX/USAX
2021-02-01 16:36:18 -05:00
Lioncash
21e404d3ab
thumb32: Implement SASX/UASX
2021-02-01 16:31:25 -05:00
Lioncash
d529417875
thumb32: Implement SADD16/UADD16
2021-02-01 16:19:33 -05:00
merry
0e26e8a531
Merge pull request #569 from lioncash/t32-misc
...
thumb32: Implement miscellaneous category instructions
2021-02-01 21:06:36 +00:00
Lioncash
36fc596a51
thumb32: Implement QADD
2021-02-01 15:44:09 -05:00
Lioncash
cd6e4c7afd
thumb32: Implement QSUB
2021-02-01 15:42:14 -05:00
Lioncash
65365ad2a3
thumb32: Implement QDADD
2021-02-01 15:39:39 -05:00
Lioncash
d96c8c662b
thumb32: Implement QDSUB
2021-02-01 15:35:09 -05:00
Lioncash
c60cf921ee
thumb32: Implement REV
2021-02-01 15:30:40 -05:00
Lioncash
0304dc7ce4
thumb32: Implement REV16
2021-02-01 15:27:31 -05:00
Lioncash
cee31c5274
thumb32: Implement RBIT
2021-02-01 15:20:24 -05:00
Lioncash
e2bc7eeb93
thumb32: Implement REVSH
2021-02-01 15:16:53 -05:00
MerryMage
e01583abba
A64/system: Reorder fields of SystemRegisterEncoding
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Matches manual, which allows for easier verification of correctness.
2021-02-01 20:01:39 +00:00
Lioncash
1ad99bb9b5
thumb32: Implement SEL
2021-02-01 15:01:21 -05:00
Lioncash
8d53048750
thumb32: Implement CLZ
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Also fleshes out the generator to allow for generating thumb32
instructions as well.
2021-02-01 14:54:04 -05:00
MerryMage
f2345c1590
A64/system: Implement MSR/MRS for NZCV
2021-02-01 19:52:49 +00:00
bunnei
de389968eb
A32: Add hook_isb option.
2021-01-28 20:47:39 -08:00
MerryMage
0f27368fda
A64: Add hook_isb option
2021-01-26 23:41:21 +00:00
MerryMage
3806284cbe
emit_x64{,_vector}_floating_point: Fix non-FMA execution
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Avoid repeated calls to GetArgumentInfo
2021-01-02 20:40:32 +00:00
MerryMage
6023bcd8ad
emit_x64_data_processing: Fix signed/unsigned warning
2021-01-02 20:12:48 +00:00
MerryMage
c15917b350
backend/x64: Add further Unsafe_InaccurateNaN locations
2021-01-02 20:12:48 +00:00
MerryMage
f9ccf91b94
Add Unsafe_InaccurateNaN optimization to all fma instructions
2021-01-02 17:22:50 +00:00
MerryMage
8c4463a0c1
emit_x64_data_processing: EmitSub: Use cmp where possible
2021-01-01 19:37:47 +00:00
MerryMage
e926f0b393
emit_x64_data_processing: Minor optimization for immediates in EmitSub
2021-01-01 13:35:01 +00:00
MerryMage
eeeafaf5fb
Introduce Unsafe_InaccurateNaN
2021-01-01 07:18:05 +00:00
ReinUsesLisp
4a9a0d07f7
backend/{a32,a64}_emit_x64: Add config entry to mask page table pointers
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Add config entry to mask out the lower bits in page table pointers.
This is intended to allow users of Dynarmic to pack small integers
inside pointers and update the pair atomically without locks.
These lower bits can be masked out due to the expected alignment in
pointers inside the page table.
For the given usage, using AND on the pointer acts the same way as a
TEST instruction. That said when the mask value is zero, TEST is still
emitted to keep the same behavior.
2020-12-29 19:16:46 +00:00
MerryMage
42059edca4
decoder_detail: Fix bit_position and one unused warnings in GetArgInfo
2020-12-28 23:34:23 +00:00
MerryMage
b47e5ea1e1
emit_x64_data_processing: Use BMI2 shifts where possible
2020-12-28 22:42:51 +00:00
ReinUsesLisp
ba6654b0e7
location_descriptor: Fix compare operator for single stepping
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Compare `single_stepping` with the other's value instead of comparing it
with the local value.
2020-12-01 09:11:40 +00:00
Wunk
3e932ca55d
emit_x64_vector: Fix ArithmeticShiftRightByte zero_extend constant
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Should be shifting in _bytes_ of `0x80`. Not bits.
2020-11-09 09:47:51 -08:00
Wunkolo
ec52922dae
emit_x64_vector: Use explicit 64-bit mask constant
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Exchange `~0ull` with `0xFFFFFFFFFFFFFFFF` when generating
the `zero_extend` constant.
2020-11-07 15:29:12 +00:00
Wunkolo
490160ef43
emit_x64_vector: GNFI implementation of ArithmeticShiftRightByte
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The bit-matrix is generated up-front and added to the constant-pool.
I'm using an embedded 64-bit broadcast here(m64bcst) which is the particular
EVEX encoded version of the instruction with AVX512VL+GNFI.
If it ever really matters, then we would ideally detect specific host
features like bare-GFNI and specific subsets of AVX512 and emit
the assembly based on that rather than by the entire Icelake uarch.
2020-11-07 15:29:12 +00:00
Wunkolo
7df235aefb
emit_x64_vector: GNFI implementation of EmitVectorLogicalShiftLeft8
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Same principle as EmitVectorLogicalShiftRight8. An 8x8 galois identity
matrix is bit-shfited to allow for arbitrary 8-bit-lane shifts.
2020-11-07 15:29:12 +00:00
