bunnei
|
4b09c0d032
|
TranslateArm: Implement QADD8 and UQADD8.
|
2016-08-12 19:00:44 +01:00 |
|
bunnei
|
127fbe99cb
|
TranslateArm: Implement QSUB8.
|
2016-08-12 19:00:44 +01:00 |
|
bunnei
|
86fe29c6d2
|
TranslateArm: Implement UQSUB8.
|
2016-08-12 19:00:44 +01:00 |
|
MerryMage
|
b4c586d5ef
|
TranslateArm: VSTR: Correct behaviour in big-endian mode
|
2016-08-10 16:43:37 +01:00 |
|
bunnei
|
8e8db6e137
|
TranslateArm: Implement VSTR.
|
2016-08-10 15:01:23 +01:00 |
|
MerryMage
|
df39308e03
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
|
2016-08-09 22:57:20 +01:00 |
|
MerryMage
|
b3bb1d5048
|
Tests: Tidy up ARM fuzz tests
|
2016-08-07 21:55:38 +01:00 |
|
MerryMage
|
4dcd1d1859
|
Arm: BLX is UNPREDICTABLE when Rm is PC
|
2016-08-07 20:50:33 +01:00 |
|
MerryMage
|
1af5bef32c
|
TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
|
2016-08-07 20:40:31 +01:00 |
|
MerryMage
|
3a465ba4a8
|
VFP: Implement VLDR
|
2016-08-07 19:59:35 +01:00 |
|
MerryMage
|
a2c2db277b
|
VFP: Implement VMOV (all variants)
|
2016-08-07 19:25:12 +01:00 |
|
Tillmann Karras
|
55204a80d0
|
Implement SMMLA, SMMLS, SMMUL
|
2016-08-06 21:17:11 +01:00 |
|
Tillmann Karras
|
81d9d4b012
|
Add Subv's sign/zero extension tests
|
2016-08-06 21:17:11 +01:00 |
|
Tillmann Karras
|
a281fcc744
|
Fix printf
|
2016-08-06 21:17:11 +01:00 |
|
MerryMage
|
9ab7626374
|
Tests/VFP: Add tests for VADD.F32
|
2016-08-06 20:03:15 +01:00 |
|
MerryMage
|
4b31ea25a7
|
VFP: Implement VADD.{F32,F64}
|
2016-08-06 20:03:15 +01:00 |
|
bunnei
|
a5e2116e12
|
fuzz_arm: Log write records on failure.
|
2016-08-05 20:04:57 -04:00 |
|
MerryMage
|
640ce48baa
|
VFP: Implement {Get,Set}ExtendedRegister{32,64}
|
2016-08-05 19:06:10 +01:00 |
|
MerryMage
|
6f6f60c61b
|
tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined
|
2016-08-05 16:04:16 +01:00 |
|
Tillmann Karras
|
eb2e6e8bea
|
Implement some multiplies
|
2016-08-05 02:09:54 +01:00 |
|
Tillmann Karras
|
a97668ead4
|
Simplify ARM fuzz tests
|
2016-08-05 02:09:30 +01:00 |
|
Tillmann Karras
|
023643b4fa
|
Disable load/store tests for now
I don't feel like debugging that right now.
|
2016-08-05 02:09:27 +01:00 |
|
Tillmann Karras
|
ab383b4be5
|
Break tests by fixing them
|
2016-08-05 02:08:41 +01:00 |
|
Tillmann Karras
|
af27ef8d6c
|
Optionally disassemble x86_64 code using LLVM
|
2016-08-05 02:08:41 +01:00 |
|
Tillmann Karras
|
dacaeadb6a
|
Raise SIGTRAP on non-Windows
|
2016-08-03 00:44:08 +01:00 |
|
MerryMage
|
64c17a2489
|
tests/FuzzArm: Print out IR upon failure
|
2016-08-02 13:48:06 +01:00 |
|
MerryMage
|
5fbfc6c155
|
Implement some simple IR optimizations (get/set eliminiation and DCE)
|
2016-07-21 21:48:45 +01:00 |
|
Subv
|
fce8f75077
|
Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC.
|
2016-07-18 16:13:33 -05:00 |
|
Subv
|
426ffc9971
|
Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH.
These tests do not test the behavior of writing to the PC.
|
2016-07-18 16:13:02 -05:00 |
|
Subv
|
c330d9e0e3
|
Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests.
|
2016-07-18 16:10:35 -05:00 |
|
MerryMage
|
dfef65d98f
|
Implement thumb POP instruction
|
2016-07-18 17:37:48 +01:00 |
|
MerryMage
|
c18a3eeab4
|
Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
|
2016-07-18 10:38:22 +01:00 |
|
Subv
|
0cdf5fe751
|
Implemented ARM REV and REVSH instructions, with tests.
|
2016-07-17 14:45:42 -05:00 |
|
MerryMage
|
866dce0f23
|
tests/Thumb: Add revsh (thumb) test
|
2016-07-16 19:22:57 +01:00 |
|
MerryMage
|
4b1c27e64f
|
Implement arm_ADC_imm
|
2016-07-14 20:02:41 +01:00 |
|
MerryMage
|
07eaf100ba
|
Reorganise src/frontend: Add subdirectories disassembler and translate
|
2016-07-14 14:39:43 +01:00 |
|
MerryMage
|
8449deb0bc
|
MSVC support
|
2016-07-12 13:28:09 +01:00 |
|
MerryMage
|
65d27f3486
|
tests: Add some Arm tests
|
2016-07-12 09:12:56 +01:00 |
|