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TranslateArm: VSTR: Correct behaviour in big-endian mode

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This commit is contained in:
MerryMage 2016-08-10 16:43:37 +01:00
parent 945498a16a
commit b4c586d5ef
2 changed files with 11 additions and 7 deletions
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7
src/frontend/translate/translate_arm/vfp2.cpp
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@ -388,8 +388,11 @@ bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd
auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
if (sz) {
auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d));
ir.WriteMemory32(address, ir.LeastSignificantWord(d_u64));
ir.WriteMemory32(ir.Add(address, ir.Imm32(4)), ir.MostSignificantWord(d_u64).result);
auto lo = ir.LeastSignificantWord(d_u64);
auto hi = ir.MostSignificantWord(d_u64).result;
if (ir.current_location.EFlag()) std::swap(lo, hi);
ir.WriteMemory32(address, lo);
ir.WriteMemory32(ir.Add(address, ir.Imm32(4)), hi);
} else {
ir.WriteMemory32(address, ir.TransferFromFP32(ir.GetExtendedRegister(d)));
}

11
tests/arm/fuzz_arm.cpp
View file

@ -424,13 +424,14 @@ TEST_CASE("VFP: VMOV", "[JitX64][vfp]") {
TEST_CASE("VFP: VMOV (reg), VLDR, VSTR", "[JitX64][vfp]") {
const std::array<InstructionGenerator, 3> instructions = {{
InstructionGenerator("cccc11101D110000dddd101z01M0mmmm"),
InstructionGenerator("cccc1101UD01nnnndddd101zvvvvvvvv"),
InstructionGenerator("cccc1101UD00nnnndddd101zvvvvvvvv"),
const std::array<InstructionGenerator, 4> instructions = {{
InstructionGenerator("1111000100000001000000e000000000"), // SETEND
InstructionGenerator("cccc11101D110000dddd101z01M0mmmm"), // VMOV (reg)
InstructionGenerator("cccc1101UD01nnnndddd101zvvvvvvvv"), // VLDR
InstructionGenerator("cccc1101UD00nnnndddd101zvvvvvvvv"), // VSTR
}};
FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {
FuzzJitArm(5, 6, 10000, [&instructions]() -> u32 {
return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
});
}