suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

TranslateArm: Implement VSTR.

Browse source
This commit is contained in:
bunnei 2016-08-10 15:01:23 +01:00 committed by MerryMage
parent df39308e03
commit 8e8db6e137
6 changed files with 29 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/CMakeLists.txt
View file

@ -59,6 +59,7 @@ set(HEADERS
frontend/decoder/decoder_detail.h
frontend/decoder/thumb16.h
frontend/decoder/thumb32.h
frontend/decoder/vfp2.h
frontend/disassembler/disassembler.h
frontend/ir/ir.h
frontend/ir/ir_emitter.h

1
src/frontend/decoder/vfp2.h
View file

@ -100,6 +100,7 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
// VSTMDB
// VPUSH
INST(&V::vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv"),
INST(&V::vfp2_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv"),
// VLDM
// VLDMDB
// VPOP

5
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -828,6 +828,11 @@ public:
u32 imm32 = imm8 << 2;
return Common::StringFromFormat("vldr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32);
}
std::string vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2;
return Common::StringFromFormat("vstr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32);
}
};
std::string DisassembleArm(u32 instruction) {

1
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -353,6 +353,7 @@ struct ArmTranslatorVisitor final {
// Floating-point load-store instructions
bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
};
} // namespace Arm

18
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -379,5 +379,23 @@ bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd
return true;
}
bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2;
ExtReg d = ToExtReg(sz, Vd, D);
// VSTR <{S,D}d>, [<Rn>, #+/-<imm32>]
if (ConditionPassed(cond)) {
auto base = n == Reg::PC ? ir.Imm32(ir.AlignPC(4)) : ir.GetRegister(n);
auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
if (sz) {
auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d));
ir.WriteMemory32(address, ir.LeastSignificantWord(d_u64));
ir.WriteMemory32(ir.Add(address, ir.Imm32(4)), ir.MostSignificantWord(d_u64).result);
} else {
ir.WriteMemory32(address, ir.TransferFromFP32(ir.GetExtendedRegister(d)));
}
}
return true;
}
} // namespace Arm
} // namespace Dynarmic

5
tests/arm/fuzz_arm.cpp
View file

@ -423,10 +423,11 @@ TEST_CASE("VFP: VMOV", "[JitX64][vfp]") {
}
TEST_CASE("VFP: VMOV (reg), VLDR", "[JitX64][vfp]") {
const std::array<InstructionGenerator, 2> instructions = {{
TEST_CASE("VFP: VMOV (reg), VLDR, VSTR", "[JitX64][vfp]") {
const std::array<InstructionGenerator, 3> instructions = {{
InstructionGenerator("cccc11101D110000dddd101z01M0mmmm"),
InstructionGenerator("cccc1101UD01nnnndddd101zvvvvvvvv"),
InstructionGenerator("cccc1101UD00nnnndddd101zvvvvvvvv"),
}};
FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {