suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

VFP: Implement VLDR

Browse source
This commit is contained in:
MerryMage 2016-08-07 19:59:35 +01:00
parent a2c2db277b
commit 3a465ba4a8
5 changed files with 40 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/decoder/vfp2.h
View file

@ -99,7 +99,7 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
// VSTM
// VSTMDB
// VPUSH
// VLDR
INST(&V::vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv"),
// VLDM
// VLDMDB
// VPOP

5
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -653,6 +653,11 @@ public:
std::string vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return Common::StringFromFormat("vsqrt%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
}
std::string vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2;
return Common::StringFromFormat("vldr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32);
}
};
std::string DisassembleArm(u32 instruction) {

3
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -344,6 +344,9 @@ struct ArmTranslatorVisitor final {
bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
// Floating-point load-store instructions
bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
};
} // namespace Arm

19
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -360,5 +360,24 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo
return true;
}
bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2;
ExtReg d = ToExtReg(sz, Vd, D);
// VLDR <{S,D}d>, [<Rn>, #+/-<imm32>]
if (ConditionPassed(cond)) {
auto base = n == Reg::PC ? ir.Imm32(ir.AlignPC(4)) : ir.GetRegister(n);
auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
if (sz) {
auto lo = ir.ReadMemory32(address);
auto hi = ir.ReadMemory32(ir.Add(address, ir.Imm32(4)));
if (ir.current_location.EFlag()) std::swap(lo, hi);
ir.SetExtendedRegister(d, ir.TransferToFP64(ir.Pack2x32To1x64(lo, hi)));
} else {
ir.SetExtendedRegister(d, ir.TransferToFP32(ir.ReadMemory32(address)));
}
}
return true;
}
} // namespace Arm
} // namespace Dynarmic

12
tests/arm/fuzz_arm.cpp
View file

@ -419,6 +419,18 @@ TEST_CASE("VFP: VMOV", "[JitX64][vfp]") {
});
}
TEST_CASE("VFP: VMOV (reg), VLDR", "[JitX64][vfp]") {
const std::array<InstructionGenerator, 2> instructions = {{
InstructionGenerator("cccc11101D110000dddd101z01M0mmmm"),
InstructionGenerator("cccc1101UD01nnnndddd101zvvvvvvvv"),
}};
FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {
return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
});
}
TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
const std::array<InstructionGenerator, 16> imm_instructions = {
{