2016-07-01 15:01:06 +02:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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2016-08-17 16:53:36 +02:00
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#include "common/common_types.h"
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#include "frontend/ir/basic_block.h"
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2016-09-05 12:54:09 +02:00
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#include "frontend/ir/location_descriptor.h"
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2016-08-17 16:53:36 +02:00
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#include "frontend/ir/terminal.h"
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#include "frontend/ir/value.h"
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// ARM JIT Microinstruction Intermediate Representation
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//
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// This intermediate representation is an SSA IR. It is designed primarily for analysis,
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// though it can be lowered into a reduced form for interpretation. Each IR node (Value)
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// is a microinstruction of an idealised ARM CPU. The choice of microinstructions is made
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// not based on any existing microarchitecture but on ease of implementation.
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2016-07-01 15:01:06 +02:00
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2018-01-26 14:51:48 +01:00
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namespace Dynarmic::IR {
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2016-07-01 15:01:06 +02:00
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2016-09-03 22:48:03 +02:00
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enum class Opcode;
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2018-01-05 22:47:23 +01:00
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template <typename T>
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struct ResultAndCarry {
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T result;
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U1 carry;
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};
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template <typename T>
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struct ResultAndOverflow {
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T result;
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U1 overflow;
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};
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template <typename T>
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struct ResultAndCarryAndOverflow {
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T result;
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U1 carry;
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U1 overflow;
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};
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template <typename T>
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struct ResultAndGE {
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T result;
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U32 ge;
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};
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2016-08-12 19:17:31 +02:00
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/**
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* Convenience class to construct a basic block of the intermediate representation.
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* `block` is the resulting block.
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* The user of this class updates `current_location` as appropriate.
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*/
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2018-01-01 16:47:56 +01:00
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class IREmitter {
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2016-07-01 15:01:06 +02:00
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public:
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2018-01-27 00:30:17 +01:00
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explicit IREmitter(Block& block) : block(block), insertion_point(block.end()) {}
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2016-07-04 15:37:50 +02:00
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2018-01-12 20:34:25 +01:00
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Block& block;
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2016-07-01 15:01:06 +02:00
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2018-04-02 19:58:35 +02:00
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U1 Imm1(bool value) const;
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U8 Imm8(u8 value) const;
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U16 Imm16(u16 value) const;
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U32 Imm32(u32 value) const;
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U64 Imm64(u64 value) const;
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2016-08-25 18:36:42 +02:00
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2018-01-01 17:19:43 +01:00
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void PushRSB(const LocationDescriptor& return_location);
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2018-01-05 22:47:23 +01:00
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U64 Pack2x32To1x64(const U32& lo, const U32& hi);
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2018-02-13 13:50:50 +01:00
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U128 Pack2x64To1x128(const U64& lo, const U64& hi);
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2018-01-05 22:47:23 +01:00
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U32 LeastSignificantWord(const U64& value);
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ResultAndCarry<U32> MostSignificantWord(const U64& value);
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2018-01-07 12:31:20 +01:00
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U16 LeastSignificantHalf(U32U64 value);
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U8 LeastSignificantByte(U32U64 value);
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2018-01-05 22:47:23 +01:00
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U1 MostSignificantBit(const U32& value);
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U1 IsZero(const U32& value);
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2018-01-07 17:33:02 +01:00
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U1 IsZero(const U64& value);
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U1 IsZero(const U32U64& value);
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U1 TestBit(const U32U64& value, const U8& bit);
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2018-01-18 12:36:48 +01:00
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U32 ConditionalSelect(Cond cond, const U32& a, const U32& b);
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U64 ConditionalSelect(Cond cond, const U64& a, const U64& b);
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2018-02-05 00:07:51 +01:00
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NZCV ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b);
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2018-01-18 12:36:48 +01:00
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U32U64 ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b);
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2018-01-05 22:47:23 +01:00
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2018-02-03 14:34:40 +01:00
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NZCV NZCVFromPackedFlags(const U32& a);
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2018-01-07 12:31:20 +01:00
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// This pseudo-instruction may only be added to instructions that support it.
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NZCV NZCVFrom(const Value& value);
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2018-01-05 22:47:23 +01:00
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ResultAndCarry<U32> LogicalShiftLeft(const U32& value_in, const U8& shift_amount, const U1& carry_in);
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ResultAndCarry<U32> LogicalShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in);
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ResultAndCarry<U32> ArithmeticShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in);
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ResultAndCarry<U32> RotateRight(const U32& value_in, const U8& shift_amount, const U1& carry_in);
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2018-01-22 23:40:00 +01:00
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U32 LogicalShiftLeft(const U32& value_in, const U8& shift_amount);
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U64 LogicalShiftLeft(const U64& value_in, const U8& shift_amount);
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2018-01-07 01:11:57 +01:00
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U32U64 LogicalShiftLeft(const U32U64& value_in, const U8& shift_amount);
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2018-01-22 23:40:00 +01:00
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U32 LogicalShiftRight(const U32& value_in, const U8& shift_amount);
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U64 LogicalShiftRight(const U64& value_in, const U8& shift_amount);
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2018-01-07 01:11:57 +01:00
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U32U64 LogicalShiftRight(const U32U64& value_in, const U8& shift_amount);
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U32U64 ArithmeticShiftRight(const U32U64& value_in, const U8& shift_amount);
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U32U64 RotateRight(const U32U64& value_in, const U8& shift_amount);
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2018-01-05 22:47:23 +01:00
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ResultAndCarry<U32> RotateRightExtended(const U32& value_in, const U1& carry_in);
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2018-01-07 12:31:20 +01:00
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ResultAndCarryAndOverflow<U32> AddWithCarry(const U32& a, const U32& b, const U1& carry_in);
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ResultAndCarryAndOverflow<U32> SubWithCarry(const U32& a, const U32& b, const U1& carry_in);
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U32U64 AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in);
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U32U64 SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in);
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2018-01-07 01:11:57 +01:00
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U32U64 Add(const U32U64& a, const U32U64& b);
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2018-01-07 12:31:20 +01:00
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U32U64 Sub(const U32U64& a, const U32U64& b);
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2018-01-23 15:51:57 +01:00
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U32U64 Mul(const U32U64& a, const U32U64& b);
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2018-01-27 17:32:07 +01:00
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U64 UnsignedMultiplyHigh(const U64& a, const U64& b);
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U64 SignedMultiplyHigh(const U64& a, const U64& b);
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2018-01-24 13:36:39 +01:00
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U32U64 UnsignedDiv(const U32U64& a, const U32U64& b);
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U32U64 SignedDiv(const U32U64& a, const U32U64& b);
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2018-01-07 13:52:12 +01:00
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U32U64 And(const U32U64& a, const U32U64& b);
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U32U64 Eor(const U32U64& a, const U32U64& b);
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U32U64 Or(const U32U64& a, const U32U64& b);
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U32U64 Not(const U32U64& a);
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2018-01-07 12:31:20 +01:00
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U32 SignExtendToWord(const UAny& a);
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U64 SignExtendToLong(const UAny& a);
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2018-01-05 22:47:23 +01:00
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U32 SignExtendByteToWord(const U8& a);
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2018-01-07 12:31:20 +01:00
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U32 SignExtendHalfToWord(const U16& a);
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U64 SignExtendWordToLong(const U32& a);
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U32 ZeroExtendToWord(const UAny& a);
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U64 ZeroExtendToLong(const UAny& a);
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2018-01-24 16:54:11 +01:00
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U128 ZeroExtendToQuad(const UAny& a);
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2018-01-05 22:47:23 +01:00
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U32 ZeroExtendByteToWord(const U8& a);
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2018-01-07 12:31:20 +01:00
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U32 ZeroExtendHalfToWord(const U16& a);
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U64 ZeroExtendWordToLong(const U32& a);
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2018-01-07 17:33:02 +01:00
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U32 IndeterminateExtendToWord(const UAny& a);
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U64 IndeterminateExtendToLong(const UAny& a);
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2018-01-05 22:47:23 +01:00
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U32 ByteReverseWord(const U32& a);
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U16 ByteReverseHalf(const U16& a);
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U64 ByteReverseDual(const U64& a);
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2018-01-22 16:51:40 +01:00
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U32U64 CountLeadingZeros(const U32U64& a);
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2018-01-26 17:49:08 +01:00
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U32U64 ExtractRegister(const U32U64& a, const U32U64& b, const U8& lsb);
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2018-01-05 22:47:23 +01:00
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ResultAndOverflow<U32> SignedSaturatedAdd(const U32& a, const U32& b);
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ResultAndOverflow<U32> SignedSaturatedSub(const U32& a, const U32& b);
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ResultAndOverflow<U32> UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to);
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ResultAndOverflow<U32> SignedSaturation(const U32& a, size_t bit_size_to_saturate_to);
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ResultAndGE<U32> PackedAddU8(const U32& a, const U32& b);
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ResultAndGE<U32> PackedAddS8(const U32& a, const U32& b);
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ResultAndGE<U32> PackedAddU16(const U32& a, const U32& b);
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ResultAndGE<U32> PackedAddS16(const U32& a, const U32& b);
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ResultAndGE<U32> PackedSubU8(const U32& a, const U32& b);
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ResultAndGE<U32> PackedSubS8(const U32& a, const U32& b);
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ResultAndGE<U32> PackedSubU16(const U32& a, const U32& b);
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ResultAndGE<U32> PackedSubS16(const U32& a, const U32& b);
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ResultAndGE<U32> PackedAddSubU16(const U32& a, const U32& b);
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ResultAndGE<U32> PackedAddSubS16(const U32& a, const U32& b);
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ResultAndGE<U32> PackedSubAddU16(const U32& a, const U32& b);
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ResultAndGE<U32> PackedSubAddS16(const U32& a, const U32& b);
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U32 PackedHalvingAddU8(const U32& a, const U32& b);
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U32 PackedHalvingAddS8(const U32& a, const U32& b);
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U32 PackedHalvingSubU8(const U32& a, const U32& b);
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U32 PackedHalvingSubS8(const U32& a, const U32& b);
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U32 PackedHalvingAddU16(const U32& a, const U32& b);
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U32 PackedHalvingAddS16(const U32& a, const U32& b);
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U32 PackedHalvingSubU16(const U32& a, const U32& b);
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U32 PackedHalvingSubS16(const U32& a, const U32& b);
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U32 PackedHalvingAddSubU16(const U32& a, const U32& b);
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U32 PackedHalvingAddSubS16(const U32& a, const U32& b);
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U32 PackedHalvingSubAddU16(const U32& a, const U32& b);
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U32 PackedHalvingSubAddS16(const U32& a, const U32& b);
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U32 PackedSaturatedAddU8(const U32& a, const U32& b);
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U32 PackedSaturatedAddS8(const U32& a, const U32& b);
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U32 PackedSaturatedSubU8(const U32& a, const U32& b);
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U32 PackedSaturatedSubS8(const U32& a, const U32& b);
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U32 PackedSaturatedAddU16(const U32& a, const U32& b);
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U32 PackedSaturatedAddS16(const U32& a, const U32& b);
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U32 PackedSaturatedSubU16(const U32& a, const U32& b);
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U32 PackedSaturatedSubS16(const U32& a, const U32& b);
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U32 PackedAbsDiffSumS8(const U32& a, const U32& b);
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U32 PackedSelect(const U32& ge, const U32& a, const U32& b);
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2018-01-25 18:51:45 +01:00
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U32 CRC32Castagnoli8(const U32& a, const U32& b);
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U32 CRC32Castagnoli16(const U32& a, const U32& b);
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U32 CRC32Castagnoli32(const U32& a, const U32& b);
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U32 CRC32Castagnoli64(const U32& a, const U64& b);
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2018-01-28 07:41:58 +01:00
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U32 CRC32ISO8(const U32& a, const U32& b);
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U32 CRC32ISO16(const U32& a, const U32& b);
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U32 CRC32ISO32(const U32& a, const U32& b);
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U32 CRC32ISO64(const U32& a, const U64& b);
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2018-01-25 18:51:45 +01:00
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2018-02-03 23:20:21 +01:00
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U128 AESDecryptSingleRound(const U128& a);
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U128 AESEncryptSingleRound(const U128& a);
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2018-01-30 13:56:18 +01:00
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U128 AESInverseMixColumns(const U128& a);
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U128 AESMixColumns(const U128& a);
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2018-05-07 14:29:12 +02:00
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U8 SM4AccessSubstitutionBox(const U8& a);
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2018-01-24 16:54:56 +01:00
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UAny VectorGetElement(size_t esize, const U128& a, size_t index);
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2018-02-02 22:00:12 +01:00
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U128 VectorSetElement(size_t esize, const U128& a, size_t index, const UAny& elem);
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2018-04-02 22:27:04 +02:00
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U128 VectorAbs(size_t esize, const U128& a);
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2018-02-10 11:18:10 +01:00
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U128 VectorAdd(size_t esize, const U128& a, const U128& b);
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2018-01-21 19:27:06 +01:00
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U128 VectorAnd(const U128& a, const U128& b);
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2018-02-11 00:27:46 +01:00
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U128 VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift_amount);
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2018-02-10 11:18:10 +01:00
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U128 VectorBroadcast(size_t esize, const UAny& a);
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U128 VectorBroadcastLower(size_t esize, const UAny& a);
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2018-02-10 10:15:01 +01:00
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U128 VectorEor(const U128& a, const U128& b);
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2018-04-24 17:58:01 +02:00
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U128 VectorDeinterleaveEven(size_t esize, const U128& a, const U128& b);
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U128 VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b);
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2018-02-10 11:18:10 +01:00
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U128 VectorEqual(size_t esize, const U128& a, const U128& b);
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2018-04-02 22:52:46 +02:00
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U128 VectorExtract(const U128& a, const U128& b, size_t position);
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U128 VectorExtractLower(const U128& a, const U128& b, size_t position);
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2018-02-13 19:20:00 +01:00
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U128 VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorGreaterEqualUnsigned(size_t esize, const U128& a, const U128& b);
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2018-02-13 15:06:54 +01:00
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U128 VectorGreaterSigned(size_t esize, const U128& a, const U128& b);
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2018-02-13 19:20:00 +01:00
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U128 VectorGreaterUnsigned(size_t esize, const U128& a, const U128& b);
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2018-05-04 14:22:14 +02:00
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U128 VectorHalvingAddSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128& b);
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2018-05-07 18:07:56 +02:00
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U128 VectorHalvingSubSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128& b);
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2018-02-10 11:18:10 +01:00
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U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b);
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2018-03-29 22:11:14 +02:00
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U128 VectorInterleaveUpper(size_t esize, const U128& a, const U128& b);
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2018-02-13 19:20:00 +01:00
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U128 VectorLessEqualSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorLessEqualUnsigned(size_t esize, const U128& a, const U128& b);
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U128 VectorLessSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorLessUnsigned(size_t esize, const U128& a, const U128& b);
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2018-02-10 11:18:10 +01:00
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U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount);
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2018-02-10 12:05:22 +01:00
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U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount);
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2018-04-30 16:01:57 +02:00
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U128 VectorLogicalVShiftSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorLogicalVShiftUnsigned(size_t esize, const U128& a, const U128& b);
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2018-02-13 18:56:46 +01:00
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U128 VectorMaxSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorMaxUnsigned(size_t esize, const U128& a, const U128& b);
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U128 VectorMinSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorMinUnsigned(size_t esize, const U128& a, const U128& b);
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2018-02-11 11:18:29 +01:00
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U128 VectorMultiply(size_t esize, const U128& a, const U128& b);
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2018-02-10 17:47:36 +01:00
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U128 VectorNarrow(size_t original_esize, const U128& a);
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2018-02-10 10:15:01 +01:00
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U128 VectorNot(const U128& a);
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U128 VectorOr(const U128& a, const U128& b);
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2018-02-10 11:18:10 +01:00
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U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b);
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U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b);
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2018-02-11 12:43:51 +01:00
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U128 VectorPopulationCount(const U128& a);
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2018-04-03 14:46:01 +02:00
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U128 VectorReverseBits(const U128& a);
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2018-04-10 20:36:35 +02:00
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U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount);
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U128 VectorRotateRight(size_t esize, const U128& a, u8 amount);
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2018-03-18 01:32:07 +01:00
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U128 VectorShuffleHighHalfwords(const U128& a, u8 mask);
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U128 VectorShuffleLowHalfwords(const U128& a, u8 mask);
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U128 VectorShuffleWords(const U128& a, u8 mask);
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2018-02-11 17:24:33 +01:00
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U128 VectorSignExtend(size_t original_esize, const U128& a);
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2018-02-10 12:25:50 +01:00
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U128 VectorSub(size_t esize, const U128& a, const U128& b);
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2018-04-01 20:21:14 +02:00
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U128 VectorUnsignedAbsoluteDifference(size_t esize, const U128& a, const U128& b);
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2018-02-10 11:28:38 +01:00
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U128 VectorZeroExtend(size_t original_esize, const U128& a);
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2018-01-24 18:11:13 +01:00
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U128 VectorZeroUpper(const U128& a);
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2018-02-20 16:38:32 +01:00
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U128 ZeroVector();
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2018-01-21 18:45:43 +01:00
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2018-02-02 22:55:23 +01:00
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U32U64 FPAbs(const U32U64& a);
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U32U64 FPAdd(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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2018-02-05 13:16:01 +01:00
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NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled);
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2018-02-02 22:55:23 +01:00
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U32U64 FPDiv(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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2018-02-11 17:43:47 +01:00
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U32U64 FPMax(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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2018-02-20 15:05:14 +01:00
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U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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2018-02-11 17:43:47 +01:00
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U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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2018-02-20 15:08:46 +01:00
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U32U64 FPMinNumeric(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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2018-02-02 22:55:23 +01:00
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U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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U32U64 FPNeg(const U32U64& a);
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U32U64 FPSqrt(const U32U64& a);
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U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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2018-01-19 02:09:46 +01:00
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U32 FPDoubleToSingle(const U64& a, bool fpscr_controlled);
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U64 FPSingleToDouble(const U32& a, bool fpscr_controlled);
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U32 FPSingleToS32(const U32& a, bool round_towards_zero, bool fpscr_controlled);
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U32 FPSingleToU32(const U32& a, bool round_towards_zero, bool fpscr_controlled);
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2018-02-04 14:08:25 +01:00
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U32 FPDoubleToS32(const U64& a, bool round_towards_zero, bool fpscr_controlled);
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U32 FPDoubleToU32(const U64& a, bool round_towards_zero, bool fpscr_controlled);
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2018-01-19 02:09:46 +01:00
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U32 FPS32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_controlled);
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U32 FPU32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_controlled);
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U64 FPS32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
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U64 FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
|
2016-08-06 18:21:29 +02:00
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|
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2018-02-11 17:29:48 +01:00
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U128 FPVectorAdd(size_t esize, const U128& a, const U128& b);
|
2018-02-21 15:07:31 +01:00
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U128 FPVectorDiv(size_t esize, const U128& a, const U128& b);
|
2018-04-02 22:02:57 +02:00
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U128 FPVectorMul(size_t esize, const U128& a, const U128& b);
|
2018-02-11 13:17:53 +01:00
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U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
|
2018-04-19 21:12:00 +02:00
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|
U128 FPVectorS32ToSingle(const U128& a);
|
2018-02-11 13:17:53 +01:00
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|
|
2016-08-05 15:07:27 +02:00
|
|
|
void Breakpoint();
|
|
|
|
|
2016-08-25 18:36:42 +02:00
|
|
|
void SetTerm(const Terminal& terminal);
|
2016-07-07 11:53:09 +02:00
|
|
|
|
2018-01-27 00:30:17 +01:00
|
|
|
void SetInsertionPoint(IR::Inst* new_insertion_point);
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|
|
void SetInsertionPoint(IR::Block::iterator new_insertion_point);
|
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|
|
|
2018-01-01 16:47:56 +01:00
|
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|
protected:
|
2018-01-27 00:30:17 +01:00
|
|
|
IR::Block::iterator insertion_point;
|
|
|
|
|
2018-01-05 22:47:23 +01:00
|
|
|
template<typename T = Value, typename ...Args>
|
|
|
|
T Inst(Opcode op, Args ...args) {
|
2018-01-27 00:30:17 +01:00
|
|
|
auto iter = block.PrependNewInst(insertion_point, op, {Value(args)...});
|
|
|
|
return T(Value(&*iter));
|
2018-01-05 22:47:23 +01:00
|
|
|
}
|
2016-07-01 15:01:06 +02:00
|
|
|
};
|
|
|
|
|
2018-01-26 14:51:48 +01:00
|
|
|
} // namespace Dynarmic::IR
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