MerryMage
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edb236ab07
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Correct implementation of thumb16_SVC and arm_SVC
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2016-08-07 22:19:39 +01:00 |
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MerryMage
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a32063fa60
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EmitX64: Implement block linking
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2016-08-07 22:11:39 +01:00 |
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MerryMage
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b3bb1d5048
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Tests: Tidy up ARM fuzz tests
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2016-08-07 21:55:38 +01:00 |
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MerryMage
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328422b740
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RegAlloc: HostCall flushes all XMM regsiters
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2016-08-07 21:02:16 +01:00 |
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MerryMage
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4dcd1d1859
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Arm: BLX is UNPREDICTABLE when Rm is PC
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2016-08-07 20:50:33 +01:00 |
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MerryMage
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1af5bef32c
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TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
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2016-08-07 20:40:31 +01:00 |
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MerryMage
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939bb5c0cb
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TranslateArm: Implement NOP
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2016-08-07 20:08:31 +01:00 |
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MerryMage
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e48df9d8fd
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TranslateArm: Implement Hint instructions as NOPs
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2016-08-07 20:04:48 +01:00 |
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MerryMage
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3a465ba4a8
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VFP: Implement VLDR
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2016-08-07 19:59:35 +01:00 |
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MerryMage
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a2c2db277b
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VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
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MerryMage
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aba705f6b9
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BackendX64: Merge Routines into BlockOfCode
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2016-08-07 18:08:48 +01:00 |
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MerryMage
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0f412247ed
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VFP: Implement VSQRT
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2016-08-07 12:19:07 +01:00 |
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MerryMage
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cd8e7c0504
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VFP: Implement VNEG
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2016-08-07 12:04:21 +01:00 |
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MerryMage
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da33af5abe
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VFP: Implement VMLA, VMLS, VNMLA, VNMLS
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2016-08-07 11:49:06 +01:00 |
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MerryMage
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3f1345a1a5
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VFP: Implement VNMUL, VDIV
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2016-08-07 10:56:12 +01:00 |
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MerryMage
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12e7f2c359
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VFP: Implement VMUL
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2016-08-07 10:21:14 +01:00 |
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MerryMage
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97b5fa173f
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VFP: Implement VSUB
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2016-08-07 01:45:52 +01:00 |
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MerryMage
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ce6b5f8210
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VFP: Implement VABS
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2016-08-07 01:27:18 +01:00 |
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MerryMage
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f88b1b4c2e
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FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask
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2016-08-07 01:10:19 +01:00 |
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MerryMage
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c35f06470f
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VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1
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2016-08-06 23:01:18 +01:00 |
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MerryMage
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94b99f5949
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Common: Add an intrusive list implementation; remove use of boost::intrusive::list.
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2016-08-06 22:23:01 +01:00 |
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Tillmann Karras
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9264e2e04c
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Use XOR when loading a zero immediate
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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55204a80d0
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Implement SMMLA, SMMLS, SMMUL
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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846d07d7b5
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Add Sub64 opcode
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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b9f4f1ed0f
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Add carry support to MostSignificantWord
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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01aebcb385
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Remove *MulHi wrappers
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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5e047107a0
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Disassemble more instructions
CLZ, SEL, USAD8, USADA8, SSAT, SSAT16, USAT, USAT16, SMLAL*, SMLA*,
SMUL*, SMLAW*, SMULW*, SMLAD, SMLALD, SMLSD, SMLSLD, SMUAD, SMUSD
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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f99cb613cf
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Disassemble packs and more multiplies
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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81d9d4b012
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Add Subv's sign/zero extension tests
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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a281fcc744
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Fix printf
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2016-08-06 21:17:11 +01:00 |
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MerryMage
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7915f97d98
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TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)
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2016-08-06 20:42:06 +01:00 |
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MerryMage
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4d127c19dd
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Common: Add a memory pool implementation, remove use of boost::pool
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2016-08-06 20:41:00 +01:00 |
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MerryMage
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411e804b0d
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Interface: Forward declare Arm::LocationDescriptor
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2016-08-06 20:11:35 +01:00 |
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MerryMage
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9ab7626374
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Tests/VFP: Add tests for VADD.F32
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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4b31ea25a7
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VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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8ff414ee0e
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Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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94d5738f62
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BackendX64/Routines: Add floating-point constants
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2016-08-06 20:01:47 +01:00 |
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MerryMage
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8754728a82
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BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case
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2016-08-06 20:01:47 +01:00 |
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MerryMage
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8cc4fe8a10
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BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly
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2016-08-06 20:01:47 +01:00 |
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Merry
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cd1eef2801
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Merged in bunnei/dynarmic/load_store (pull request #9)
arm: Implement LDR/LDRB/LDRH/LDRD/STR/STRB/STRH/STRD.
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2016-08-06 14:22:45 +01:00 |
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bunnei
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2448d52394
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load_store: Use correct types for LDR/STR.
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2016-08-05 20:51:32 -04:00 |
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bunnei
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8c2300d477
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arm: Implement LDRD reg/imm instructions.
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2016-08-05 20:05:02 -04:00 |
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bunnei
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72608b7af6
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arm: Handle Cond::NV (some 3DS games use this despite being obsolete).
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2016-08-05 20:05:02 -04:00 |
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bunnei
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ec3a98cf95
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arm: Implement LDRH reg/imm instructions.
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2016-08-05 20:05:01 -04:00 |
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bunnei
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192a0fba7a
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arm: Implement LDRB reg/imm instructions.
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2016-08-05 20:05:00 -04:00 |
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bunnei
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dfb318f208
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arm: Implement STRD reg/imm instructions.
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2016-08-05 20:04:59 -04:00 |
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bunnei
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e931dc2496
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arm: Implement STRH reg/imm instructions.
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2016-08-05 20:04:58 -04:00 |
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bunnei
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9f77662b24
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arm: Implement STRB reg/imm instructions.
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2016-08-05 20:04:57 -04:00 |
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bunnei
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a5e2116e12
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fuzz_arm: Log write records on failure.
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2016-08-05 20:04:57 -04:00 |
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bunnei
|
caab1bbc7c
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arm: Implement STR reg/imm instructions.
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2016-08-05 20:04:56 -04:00 |
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