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Author SHA1 Message Date
MerryMage
d8bee60947 translate_thumb: Read-after-write in thumb16_BLX_reg 
When the instruction BLX LR is translated, BXWritePC(GetRegister(Reg::LR))
was executed after the SetRegister(Reg::LR, _) update was performed.
 2016-08-22 14:28:51 +01:00
Lioncash
1abe881921 basic_block: Add proxy member functions for the instruction list 
Currently basic block kind of acts like a 'dumb struct' which makes things
a little more verbose to write (as opposed to keeping it all in one place,
I guess). It's also a little wonky conceptually, considering a block is
composed of instructions (i.e. 'contains' them).

So providing accessors that make it act more like a container can make working
with algorithms a little nicer. It also makes the API a little more
defined.

Ideally, the list would be only available through a function, but
currently, the pool allocator is exposed, which seems somewhat odd,
considering the block itself should manage its overall allocations
(with placement new, and regular new), rather than putting that
sanitizing directly on the IR emitter (it should just care about emission,
not block state). However, recontaining that can be followed up with,
as it's very trivial to do.
 2016-08-22 13:44:56 +01:00
Lioncash
a8ba15f0d5 intrusive_list: Make Remove and IsEmpty stdlib compatible 
Makes the name match the standard library equivalents.

C++17 introduces non-member empty() which allows for nicer handling
in generic contexts. May as well make the data structure compatible with
it.
 2016-08-19 20:25:18 +01:00
Lioncash
23d190f7b0 intrusive_list: Support inserters 
Allows std::inserter, std::back_inserter, and std::front_inserter to work
with intrusive lists.
 2016-08-19 20:25:17 +01:00
MerryMage
2d6a86e43c Remove <cassert> 2016-08-19 01:53:24 +01:00
MerryMage
192a0029be ir/opcodes: Implement IR::AreTypesCompatible 
Type-checking is now occuring in more than one place.
 2016-08-19 01:34:14 +01:00
Tillmann Karras
9782e7da3f verification_pass: show type errors 2016-08-19 01:17:30 +01:00
Tillmann Karras
dad7724b86 TranlateArm: implement remaining multiplies 
SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD,
SMUAD, SMUSD
 2016-08-19 01:08:38 +01:00
MerryMage
fe15cbd50e translate_arm/parallel: Detect UNPREDICTABLE instructions 2016-08-19 00:59:07 +01:00
MerryMage
2119dfc926 translate_arm/multiply: MLA is UNPREDICTABLE when Ra == R15 2016-08-19 00:59:05 +01:00
MerryMage
0d0f4b1b4f translate_arm/load_store: Correct implementation for LDM* 2016-08-19 00:59:04 +01:00
MerryMage
4acc481463 translate_arm/load_store: Handle unpredictable instructions 
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:

a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors

I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
 2016-08-19 00:59:02 +01:00
MerryMage
5869e79b9c translate_arm: Simplify EmitImmShift and EmitRegShift 2016-08-19 00:21:31 +01:00
MerryMage
b8cf43c43e translate_arm/data_processing: Rd == R15 is unpredictable for rsr instructions 2016-08-18 18:23:05 +01:00
MerryMage
efc8d2f772 arm_translator: NV conditional is obsolete 2016-08-18 18:21:48 +01:00
MerryMage
5f7d940fde disassemble_arm: Partially implement coprocessor and hint instructions 2016-08-18 18:21:16 +01:00
MerryMage
36a916a766 decoder/arm: Correct NOP decoder 2016-08-18 18:20:29 +01:00
MerryMage
e9e7ac6e65 decoder/arm: Correct PLD decoder for v6K 2016-08-18 18:19:34 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
Lioncash
9ed9f4c565 mp: Generalize function information retrieval 
Generalizes MemFnInfo to be compatible with all function types.
Also adds type introspection for arguments, as well as helper templates for the common types supported by all partial specializations.
 2016-08-17 10:08:40 +01:00
MerryMage
7d7ac0af71 Optimization: Make SVC use RSB 2016-08-15 15:02:08 +01:00
MerryMage
6c45619aa1 Optimization: Implement terminal LinkBlockFast 2016-08-15 14:33:17 +01:00
MerryMage
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
bunnei
30f3d869cc TranslateArm: Implement VPUSH and VPOP. 2016-08-13 19:37:03 +01:00
MerryMage
960d14d18e Optimization: Implement Return Stack Buffer 2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
MerryMage
3808938c98 Fix SETEND 2016-08-11 19:15:58 +01:00
bunnei
218980cf69 load_store: Implement LDRSB and LDRSH. 2016-08-11 17:18:20 +01:00
MerryMage
0e5593ba62 TranslateArm: Implement SETEND 2016-08-11 17:15:33 +01:00
MerryMage
8964b38cf9 IR/DumpBlock: Print references to ExtRegs 2016-08-11 17:15:02 +01:00
MerryMage
b4c586d5ef TranslateArm: VSTR: Correct behaviour in big-endian mode 2016-08-10 16:43:37 +01:00
MerryMage
945498a16a DisassemblerArm: Disassemble SETEND 2016-08-10 16:15:07 +01:00
bunnei
8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
d921390928 TranslateArm: Add santity check to see if we've emitted a terminal instruction 2016-08-09 22:47:41 +01:00
MerryMage
2eec43178a IR: Opaque can be of any type 2016-08-09 22:46:44 +01:00
MerryMage
82f42d065f DisassemblerArm: Implemented disassembly of STR*/LDR* instructions 2016-08-09 22:44:42 +01:00
MerryMage
d0d51ba346 TranslateArm: Implement STM, STMDA, STMDB, STMIB 2016-08-08 22:49:11 +01:00
Tillmann Karras
5d26899ac9 Add simplified LogicalShiftRight64 IR opcode 2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5 Add support for the APSR.Q flag 2016-08-08 22:27:04 +01:00
Tillmann Karras
11e0688e5f Fix build on case-sensitive file systems 2016-08-08 22:27:03 +01:00
MerryMage
85549d7ae2 TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB 2016-08-08 22:26:06 +01:00
MerryMage
46e4864707 ArmTypes: Add RegListToString and reorganise 2016-08-08 22:20:28 +01:00
MerryMage
edb236ab07 Correct implementation of thumb16_SVC and arm_SVC 2016-08-07 22:19:39 +01:00
MerryMage
4dcd1d1859 Arm: BLX is UNPREDICTABLE when Rm is PC 2016-08-07 20:50:33 +01:00
MerryMage
1af5bef32c TranslateArm: Implement BLX (imm), BLX (reg) and BXJ 2016-08-07 20:40:31 +01:00