translate_arm/parallel: Detect UNPREDICTABLE instructions
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1 changed files with 12 additions and 0 deletions
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@ -61,6 +61,8 @@ bool ArmTranslatorVisitor::arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
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// Parallel Add/Subtract (Saturating) instructions
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bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedAddS8(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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@ -69,6 +71,8 @@ bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
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}
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bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedAddS16(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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@ -85,6 +89,8 @@ bool ArmTranslatorVisitor::arm_QSAX(Cond cond, Reg n, Reg d, Reg m) {
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}
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bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedSubS8(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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@ -93,6 +99,8 @@ bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
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}
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bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedSubS16(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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@ -125,6 +133,8 @@ bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
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}
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bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedSubU8(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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@ -133,6 +143,8 @@ bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
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}
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bool ArmTranslatorVisitor::arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedSubU16(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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