MerryMage
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7ff280827b
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A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1d0cd95b23
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A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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f6247125c0
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d74f4e35f6
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block_of_code: Increase constant pool size
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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e69288f803
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devirtualize: MinGW uses Intanium MFP ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ad428cbd7a
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callback: Properly handle calls with return pointers and simplify interface
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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15871910af
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Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7a87e3fc55
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devirtualize: Handle Windows ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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12173a8792
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travis: Switch to yuzu-emu's unicorn repository
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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a78e13ff19
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fuzz_arm: Use SCOPE_FAIL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ba4a779c62
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A32/decoder/arm: bug: Correct bitstring for SRS
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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f808a0fbde
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devirtualize: Devirtualize Itanium ABI MFPs at runtime
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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afe16fa0f3
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cast_util: Add BitCast and BitCastPointee
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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4e33629b0e
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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35a29a9665
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A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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586854117b
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Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1a7b7b541a
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8ab7d8175c
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impl: Add AdvSIMDExpandImm
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ea69cb4474
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A64: Implement SUB (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4c5871d5d5
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A64: Implement ADD (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2a0850c068
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7b33772ac6
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A64: Implement BIC (vector, register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ca43be4146
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docs: Update documentation (2018-02-05)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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eb5591859c
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A64: Implement FMOV (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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dd88cee15a
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translate/impl: Add Vpart
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cc9efd13c9
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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81713c2b77
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ef906dbbfa
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A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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44c3c2312a
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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2ee39d6b36
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A64: Implement FMOV (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b02b861242
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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5a65313236
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A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ab4664de61
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A64: Implement CCMN (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a6c6539109
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A64: Implement CCMP (register)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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22632db337
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microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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c5033b5dda
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A64: Implement CCMN (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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dd2a6684fe
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IR: Add ConditionalSelectNZCV instruction
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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12c6f841c2
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inst_gen: Make invalid_instructions a static inline variable
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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f96e83c486
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fuzz_with_unicorn: Move instruction generator vector into GenRandomInst
Keeps scope localized and prevents potential static initialization issues.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4491746eae
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A64: Implement FNEG
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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db958061a3
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A64: Implement FABS
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8765b421b7
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A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7e82d8eede
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A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2409e5d082
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b173fcf34e
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backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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56bc7825ef
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2020-04-22 20:46:13 +01:00 |
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