Merry
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a5f3164c38
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backend/arm64/reg_alloc: Handle immediates in DefineAsExisting
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2022-10-18 15:04:30 +01:00 |
|
Merry
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277f7a76e9
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arm64: Stub PushRSB
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2022-10-18 15:04:30 +01:00 |
|
Merry
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ef137dd8b9
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emit_arm64_data_processing: Correct ArithmeticShiftRight32
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2022-10-18 15:04:30 +01:00 |
|
Merry
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70d9137859
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backend/arm64/reg_alloc: Handle immediates in PrepareForCall
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2022-10-18 15:04:30 +01:00 |
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Merry
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187f89951d
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emit_arm64_data_processing: Implement Mul
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2022-10-18 15:04:30 +01:00 |
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Merry
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bf55920ce9
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backend/arm64/reg_alloc: Support multiple locks on a location
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2022-10-18 15:04:30 +01:00 |
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Merry
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6bcfaee1f4
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emit_arm64_data_processing: Implement LogicalShiftRight32
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2022-10-18 15:04:30 +01:00 |
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Merry
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7840caef6e
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emit_arm64_data_processing: Fix bug in EmitBitOp
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2022-10-18 15:04:30 +01:00 |
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Merry
|
02cfbb8b0b
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backend/arm64/reg_alloc: Generate immediates when required
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2022-10-18 15:04:30 +01:00 |
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Merry
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bdb41be0c5
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emit_arm64_data_processing: Implement ZeroExtend
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
7ed217ff77
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emit_arm64_data_processing: Implement SignExtend
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
777d9a1045
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emit_arm64_data_processing: Implement ByteReverse
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
156bcecb02
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emit_arm64_data_processing: Implement ArithmeticShiftRight32
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
a6e761daa9
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emit_arm64_a32: Fix CheckBit
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
95ae21bd41
|
backend/arm64: Fix Sub
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
46f4063952
|
backend/arm64: Implement Not
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
6ad7758165
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backend/arm64: Implement AndNot
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
fcd2bd600e
|
backend/arm64: Implement Or
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
4cff0d9977
|
backend/arm64: Implement Eor
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
4e3fd70f6e
|
backend/arm64: Implement And64
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
32e54481e7
|
github: Test arm64 backend
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
129af4f6b4
|
backend/arm64: Implement A32SetCpsrNZ
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
7056913b6b
|
backend/arm64: Implement And32
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
f97b520221
|
backend/arm64: Implement RotateRight32
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
6885f9a6d8
|
backend/arm64: Invalidation fixes
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
eaf87ec1e4
|
backend/arm64: Simple implementation of memory read/write
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
77634509b5
|
arm64/abi: Deduplicate register code
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
f3bf27c816
|
backend/arm64: Implement Devirtualize
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
6239eb5eb6
|
oaknut: dx
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
9a35946aec
|
oaknut: align
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
2e72d69268
|
backend/arm64: ABI
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
e1ad7ef482
|
oaknut: Add dw
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
f74a5f262f
|
backend/arm64/reg_alloc: RAReg is non-copyable and non-moveable
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
3a3b43b963
|
backend/arm64: Implement A32ClearExclusive
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
9bdff6a9aa
|
constant_propagation_pass: Shift with non-zero value does not require c flag as input
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
5a864f41c6
|
backend/arm64/reg_alloc: Implement DefineAsRegister
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
16701ae6d5
|
backend/arm64/reg_alloc: Use NZCV instead of magic numbers
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
ba00b3586c
|
oaknut: Add common system registers
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
c2ff75e29c
|
backend/arm64: Implement Sub
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
8ac57bd6ed
|
backend/arm64/reg_alloc: Assert on bad RAReg
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
78bc0812b9
|
backend/arm64/reg_alloc: More flag handling
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
21601764de
|
backend/arm64: Implement Add
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
679efb9c44
|
backend/arm64: Implement A32SetCpsrNZCV
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
67df13f886
|
backend/arm64: Update for new C flag representation
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
d69582f548
|
backend/arm64/reg_alloc: Tidy up HostLocInfo
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
01f28facbd
|
abi: Add Rscratch{0,1}
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
8b41755db0
|
ir_emitter: Remove unused ResultAndCarryAndOverflow structure
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
b6bb94872a
|
backend/arm64: Implement IsZero64
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
3821c4a16b
|
backend/arm64: Implement MostSignificantWord
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
ec3c597591
|
backend/arm64: Implement LeastSignificantByte
|
2022-10-18 15:04:30 +01:00 |
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