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backend/arm64: Implement And32

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Merry 2022-07-24 16:08:38 +01:00 committed by merry
parent f97b520221
commit 7056913b6b
2 changed files with 52 additions and 4 deletions
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4
src/dynarmic/backend/arm64/emit_arm64.cpp
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@ -79,6 +79,10 @@ template<>
void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
if (ctx.reg_alloc.IsValueLive(inst)) {
return;
}
auto Wvalue = ctx.reg_alloc.ReadW(args[0]);
auto flags = ctx.reg_alloc.WriteFlags(inst);
RegAlloc::Realize(Wvalue, flags);

52
src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
View file

@ -641,12 +641,56 @@ void EmitIR<IR::Opcode::SignedDiv64>(oaknut::CodeGenerator& code, EmitContext& c
ASSERT_FALSE("Unimplemented");
}
template<size_t bitsize, typename EmitFn>
static void MaybeBitImm(oaknut::CodeGenerator& code, u64 imm, EmitFn emit_fn) {
static_assert(bitsize == 32 || bitsize == 64);
if constexpr (bitsize == 32) {
imm = static_cast<u32>(imm);
}
if (oaknut::detail::encode_bit_imm(imm)) {
emit_fn(imm);
} else {
code.MOV(Rscratch0<bitsize>(), imm);
emit_fn(Rscratch0<bitsize>());
}
}
template<>
void EmitIR<IR::Opcode::And32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code;
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
ASSERT(!(nz_inst && nzcv_inst));
const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Wresult = ctx.reg_alloc.WriteW(inst);
auto Wa = ctx.reg_alloc.ReadW(args[0]);
if (flag_inst) {
auto Wflags = ctx.reg_alloc.WriteFlags(flag_inst);
if (args[1].IsImmediate()) {
RegAlloc::Realize(Wresult, Wa, Wflags);
MaybeBitImm<32>(code, args[1].GetImmediateU64(), [&](const auto& b) { code.ANDS(Wresult, Wa, b); });
} else {
auto Wb = ctx.reg_alloc.ReadW(args[1]);
RegAlloc::Realize(Wresult, Wa, Wb, Wflags);
code.ANDS(Wresult, Wb, Wb);
}
} else {
if (args[1].IsImmediate()) {
RegAlloc::Realize(Wresult, Wa);
MaybeBitImm<32>(code, args[1].GetImmediateU64(), [&](const auto& b) { code.AND(Wresult, Wa, b); });
} else {
auto Wb = ctx.reg_alloc.ReadW(args[1]);
RegAlloc::Realize(Wresult, Wa, Wb);
code.AND(Wresult, Wb, Wb);
}
}
}
template<>