MerryMage
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49cc6d7fad
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A64: Implement FDIV (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
|
c832cec96d
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Correct FPSR and FPCR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
|
147284427b
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A64: Implement USHL
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e4697b1676
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A64: Implement system register TPIDR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
|
e3da92024e
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A64: Implement system registers FPCR and FPSR
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
9e4e4e9c1d
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A64: Implement system register CNTPCT_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1e15283d00
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A64: Implement system register CTR_EL0
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
710d09471b
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IR: Add IR instruction ZeroVector
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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2721bb5ace
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emit_x64_floating_point: Add maybe_unused to preprocess parameter
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2020-04-22 20:46:15 +01:00 |
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MerryMage
|
0575e7421b
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1c9804ea07
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A64: Implement FMAXNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1dfce0894d
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constant_pool: Add frame parameter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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84f1c9b7f4
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reg_alloc: Only exchange GPRs
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6541ec064d
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emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
7c193485e1
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a64/config: Allow NaN emulation accuracy to be set
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a3df46a75a
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a64_emit_x64: Add conf to A64EmitContext
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
07520f32c3
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backend_x64: Accurately handle NaNs
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e97581d063
|
fuzz_with_unicorn: Print AArch64 disassembly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1f5b3bca43
|
Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
|
2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f3fa4a042f
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a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
8698f057d0
|
A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a6cc667509
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f45a5e17c6
|
Implement direct page table access
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd3e30c75
|
callbacks: Member functions should be const
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9f2f08db8d
|
a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c4773e85b
|
abi: Add RAX to ABI_ALL_CALLER_SAVE
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8756487554
|
A64: Partially implement MRS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd65bedfe
|
A64: Implement DSB, DMB
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2cb0a699ba
|
IR: Implement FPMax, FPMin
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
98c8e7d1af
|
IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
eae518a338
|
IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
851fc83445
|
emit_x64_vector: EmitOneArgumentFallback
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
303088a51e
|
IR: Implement VectorPopulationCount
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bf2cd92da9
|
emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b062266b8e
|
emit_x64_vector: More explicit lambda decay
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b6de612e01
|
IR: Implement VectorMultiply
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
90a053a5e4
|
emit_x64_vector: Order alphabetically
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
715ae1c229
|
IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
132c783320
|
IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1423584f9f
|
constant_pool: Allow for 128-bit constants
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
69de50a878
|
emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
cbc9f361b0
|
IR: Implement VectorSub
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b22c5961f9
|
IR: Implement VectorLogicalShiftRight
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
59ace60b03
|
IR: Implement VectorZeroExtend
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
f6247125c0
|
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
|
2020-04-22 20:46:13 +01:00 |
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