MerryMage
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5f77ab28ee
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A64: Implement SSHLL, SSHLL2
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eae518a338
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IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a90e4955ab
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CMakeLists: Ignore warnings within xbyak
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3738043e58
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A64: Implement DUP (element), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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ce7628b6b5
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f1cb5581c9
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A64: Implement FSUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b9cd345ddc
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IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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851fc83445
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emit_x64_vector: EmitOneArgumentFallback
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f378d2ef1b
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Forward declare IR::Opcode and IR::Type where possible
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c9b4f0114
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A64: Implement CNT
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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303088a51e
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IR: Implement VectorPopulationCount
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1dd2b33b87
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A64: Implement MLS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5eac3abf52
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A64: Implement MLA (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bf2cd92da9
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emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b062266b8e
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emit_x64_vector: More explicit lambda decay
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3afd2fcbad
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A64: Implement MUL (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b6de612e01
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IR: Implement VectorMultiply
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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90a053a5e4
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emit_x64_vector: Order alphabetically
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e7041d7196
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a455ff70c9
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decoder/a64: Don't rearrange unrelated decoders
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
faeb77e8c4
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A64: Implement SUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
bd106c3ae7
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A64: Implement SIMD instruction SSRA, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f58aba9871
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A64: Implement SIMD instruction SSHR, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
653c82d8f0
|
impl: Improve Vpart setter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e858ce0b35
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A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1423584f9f
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constant_pool: Allow for 128-bit constants
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
69de50a878
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
3f93c77ace
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A64: Implement SIMD instruction USRA, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
fb9d20f27f
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A64: Implement SIMD instruction USHR, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7ff280827b
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A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1d0cd95b23
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A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
f6247125c0
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d74f4e35f6
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block_of_code: Increase constant pool size
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
e69288f803
|
devirtualize: MinGW uses Intanium MFP ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ad428cbd7a
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callback: Properly handle calls with return pointers and simplify interface
|
2020-04-22 20:46:13 +01:00 |
|
FernandoS27
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15871910af
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Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7a87e3fc55
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devirtualize: Handle Windows ABI
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
12173a8792
|
travis: Switch to yuzu-emu's unicorn repository
|
2020-04-22 20:46:13 +01:00 |
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MerryMage
|
a78e13ff19
|
fuzz_arm: Use SCOPE_FAIL
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ba4a779c62
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A32/decoder/arm: bug: Correct bitstring for SRS
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
f808a0fbde
|
devirtualize: Devirtualize Itanium ABI MFPs at runtime
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
afe16fa0f3
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cast_util: Add BitCast and BitCastPointee
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
4e33629b0e
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
|
2020-04-22 20:46:13 +01:00 |
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