MerryMage
b47adaee1d
emit_x64_vector: SSSE3 implementation of EmitVectorExtract
2020-06-01 15:41:36 +01:00
MerryMage
f3845cea9a
A32: Implement ASIMD VQSUB instruction
2020-05-30 18:19:17 +01:00
MerryMage
16ff880f8f
A32: Implement ASIMD VQADD
2020-05-30 16:09:37 +01:00
MerryMage
174fbb74c5
simd_three_same: Use VectorSaturated{Signed,Unsigned}{Add,Sub} in SaturatingArithmeticOperation
2020-05-30 15:55:32 +01:00
MerryMage
4e90754873
IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub}
2020-05-30 15:55:32 +01:00
MerryMage
3a50d444dc
A32: Implement ASIMD VHSUB
2020-05-28 22:29:00 +01:00
MerryMage
205e6c5a56
A32: Implement ASIMD VRHADD
2020-05-28 22:29:00 +01:00
MerryMage
946eb03a3b
A32: Implement ASIMD VHADD
2020-05-28 22:29:00 +01:00
MerryMage
f8062345bb
asimd_two_regs_misc: Use {Get,Set}Vector
2020-05-28 21:05:30 +01:00
MerryMage
11cec1e3b6
asimd_three_same: Use {Get,Set}Vector
2020-05-28 21:05:16 +01:00
MerryMage
7d0b16de32
asimd_one_reg_modified_immediate: Use {Get,Set}Vector
2020-05-28 20:40:26 +01:00
MerryMage
cae857b8c8
verification_pass: Have an appropriate assertion message
2020-05-28 20:40:11 +01:00
MerryMage
ebddf6cca0
basic_block: Allow printing of invalid instruction pointers
2020-05-28 20:39:50 +01:00
MerryMage
07108246cf
A32/IR: Add SetVector and GetVector
2020-05-28 20:39:19 +01:00
MerryMage
e85a08ec34
CMakeLists: MSVC: Weaken warning level for externals
2020-05-26 20:52:06 +01:00
MerryMage
93c289b54f
Use tsl::robin_map and tsl::robin_set
...
Replace std::unordered_map and std::unordered_set with the above.
Better performance profile.
2020-05-26 20:51:48 +01:00
MerryMage
91578edc69
externals: Add robin-map
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Merge commit '8bf66a678af746fce336851a8ddf8fa08d358a20' as 'externals/robin-map'
2020-05-26 20:51:29 +01:00
MerryMage
8bf66a678a
Squashed 'externals/robin-map/' content from commit 5cf53c6f5
...
git-subtree-dir: externals/robin-map
git-subtree-split: 5cf53c6f5d81ba31a475f66ac4a61c6f54e476d3
2020-05-26 20:51:11 +01:00
Lioncash
c4a4bdd7de
frontend: Relocate ExtReg handling to types.h
...
Same behavior, but deduplicates the code being placed across several
files
2020-05-24 23:55:47 +01:00
Lioncash
1900df5340
frontend: Relocate advanced SIMD expansion to a common file
...
Deduplicates code a little bit.
2020-05-24 23:55:47 +01:00
Lioncash
fc112e61f2
A32: Implement ASIMD modified immediate functions
...
Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.
2020-05-24 23:55:47 +01:00
Lioncash
659d78c9c4
A32: Implement ASIMD VSWP
...
A trivial one to implement, this just swaps the contents of two
registers in place.
2020-05-22 19:43:24 +01:00
MerryMage
d0d50c4824
print_info: Use VFP and ASIMD decoders to get dynarmic name for instruction
2020-05-17 22:48:14 +01:00
MerryMage
d0075f4ea6
print_info: Use LLVM to disassemble A32
2020-05-17 22:30:46 +01:00
MerryMage
c59a127e86
opcodes: Switch from std::map to std::array
...
Optimization.
2020-05-17 17:01:39 +01:00
MerryMage
d0b45f6150
A32: Implement ARMv8 VST{1-4} (multiple)
2020-05-17 17:01:39 +01:00
Lioncash
eb332b3836
asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction
...
Now that all bitwise instructions are implemented, we can unify all of
them together using if constexpr.
2020-05-16 20:22:12 +01:00
Lioncash
f42b3ad4a0
A32: Implement ASIMD VBIF (register)
2020-05-16 20:22:12 +01:00
Lioncash
ee9a81dcba
A32: Implement ASIMD VBIT (register)
2020-05-16 20:22:12 +01:00
Lioncash
d624059ead
A32: Implement ASIMD VBSL (register)
2020-05-16 20:22:12 +01:00
Lioncash
66663cf8e7
asimd_three_same: Collapse all bitwise implementations into a single code path
...
Less code and results in only writing the parts that matter once.
2020-05-16 20:22:12 +01:00
Lioncash
4b5e3437cf
A32: Implement ASIMD VEOR (register)
2020-05-16 20:22:12 +01:00
Lioncash
67b284f6fa
A32: Implement ASIMD VORN (register)
2020-05-16 20:22:12 +01:00
Lioncash
1fdd90ca2a
A32: Implement ASIMD VORR (register)
2020-05-16 20:22:12 +01:00
Lioncash
9b93a9de46
a32_jitstate: Remove obsoleted debug assert
2020-05-16 20:22:12 +01:00
Lioncash
64fa804dd4
A32: Implement ASIMD VBIC (register)
2020-05-16 20:22:12 +01:00
Lioncash
0441ab81a1
A32: Implement ASIMD VAND (register)
2020-05-16 20:22:12 +01:00
Lioncash
1b25e867ae
asimd_load_store_structures: Simplify ToExtRegD()
...
ExtReg has a supplied operator+, so we can make use of that instead.
2020-05-16 11:27:22 -04:00
MerryMage
2169653c50
a64_emit_x64: Invalid regalloc code for EmitA64ExclusiveReadMemory128
...
Attempted to allocate args[0] after end of allocation scope
2020-05-16 14:11:23 +01:00
MerryMage
1a0bc5ba91
A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple)
2020-05-16 14:11:23 +01:00
MerryMage
e7f1a0d408
A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H}
2020-05-15 21:07:36 +01:00
Lioncash
8808b8c479
cpu_info: Make test non-allocating
...
Same behavior, but makes it non-allocating by using a constexpr
std::array instead of a std::vector.
2020-05-12 09:52:55 +01:00
Lioncash
af3b65b135
decoder_detail: Mark GetMaskAndExpect() as constexpr
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Elides quite a bit of code at runtime when constructing the decoding
tables.
2020-05-11 08:29:06 +01:00
MerryMage
59db2c191a
VFPv3: Implement VMOV (immediate)
2020-05-10 15:09:37 +01:00
MerryMage
7f77a04900
fuzz_arm: Do not test vfp_VMRS
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This may emit a vmrs *, fpscr instruction.
This results in fuzz failures due to slight inaccuracies in fpscr emulation.
2020-05-10 14:47:21 +01:00
MerryMage
3c86d58064
VFPv4: Implement VCVTB, VCVTT
2020-05-10 14:45:18 +01:00
MerryMage
010fab9a0e
VFPv4: Implement VFMA, VFMS
2020-05-10 14:20:11 +01:00
MerryMage
8e97b10acb
VFPv4: Implement VFNMS, VFNMA
2020-05-10 14:14:03 +01:00
MerryMage
6df660c889
fuzz_arm: Ensure all instructions are fuzzed
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* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
2020-05-10 13:57:39 +01:00
MerryMage
9a38c7324f
A32: Add decoders for remaining v7 instructions
2020-05-10 10:50:34 +01:00
