asimd_one_reg_modified_immediate: Use {Get,Set}Vector
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1 changed files with 21 additions and 14 deletions
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@ -16,15 +16,16 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
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return UndefinedInstruction();
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}
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const auto d_reg = ToExtRegD(Vd, D);
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const size_t regs = Q ? 2 : 1;
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const auto d_reg = ToVector(Q, Vd, D);
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const auto imm = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h));
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// VMOV
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const auto mov = [&] {
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const auto imm64 = ir.Imm64(imm);
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for (size_t i = 0; i < regs; i++) {
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ir.SetExtendedRegister(d_reg + i, imm64);
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if (Q) {
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ir.SetVector(d_reg, ir.VectorBroadcast(64, imm64));
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} else {
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ir.SetExtendedRegister(d_reg, imm64);
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}
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return true;
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};
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@ -32,8 +33,10 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
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// VMVN
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const auto mvn = [&] {
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const auto imm64 = ir.Imm64(~imm);
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for (size_t i = 0; i < regs; i++) {
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ir.SetExtendedRegister(d_reg + i, imm64);
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if (Q) {
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ir.SetVector(d_reg, ir.VectorBroadcast(64, imm64));
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} else {
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ir.SetExtendedRegister(d_reg, imm64);
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}
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return true;
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};
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@ -41,10 +44,12 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
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// VORR
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const auto orr = [&] {
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const auto imm64 = ir.Imm64(imm);
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for (size_t i = 0; i < regs; i++) {
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const auto d_index = d_reg + i;
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const auto reg_value = ir.GetExtendedRegister(d_index);
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ir.SetExtendedRegister(d_index, ir.Or(reg_value, imm64));
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if (Q) {
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const auto reg_value = ir.GetVector(d_reg);
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ir.SetVector(d_reg, ir.VectorOr(reg_value, ir.VectorBroadcast(64, imm64)));
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} else {
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const auto reg_value = ir.GetExtendedRegister(d_reg);
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ir.SetExtendedRegister(d_reg, ir.Or(reg_value, imm64));
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}
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return true;
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};
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@ -52,10 +57,12 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
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// VBIC
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const auto bic = [&] {
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const auto imm64 = ir.Imm64(~imm);
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for (size_t i = 0; i < regs; i++) {
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const auto d_index = d_reg + i;
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const auto reg_value = ir.GetExtendedRegister(d_index);
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ir.SetExtendedRegister(d_index, ir.And(reg_value, imm64));
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if (Q) {
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const auto reg_value = ir.GetVector(d_reg);
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ir.SetVector(d_reg, ir.VectorAnd(reg_value, ir.VectorBroadcast(64, imm64)));
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} else {
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const auto reg_value = ir.GetExtendedRegister(d_reg);
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ir.SetExtendedRegister(d_reg, ir.And(reg_value, imm64));
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}
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return true;
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};
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