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A32: Implement ASIMD VEOR (register)

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Lioncash 2020-05-16 13:03:40 -04:00 committed by merry
parent 67b284f6fa
commit 4b5e3437cf
3 changed files with 22 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -6,7 +6,7 @@ INST(asimd_VAND_reg, "VAND (register)", "111100100D00nnnndddd000
INST(asimd_VBIC_reg, "VBIC (register)", "111100100D01nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VORN_reg, "VORN (register)", "111100100D11nnnndddd0001NQM1mmmm") // ASIMD
//INST(asimd_VEOR_reg, "VEOR (register)", "111100110-00--------0001---1----") // ASIMD
INST(asimd_VEOR_reg, "VEOR (register)", "111100110D00nnnndddd0001NQM1mmmm") // ASIMD
//INST(asimd_VBSL, "VBSL", "111100110-01--------0001---1----") // ASIMD
//INST(asimd_VBIT, "VBIT", "111100110-10--------0001---1----") // ASIMD
//INST(asimd_VBIF, "VBIF", "111100110-11--------0001---1----") // ASIMD

20
src/frontend/A32/translate/impl/asimd_three_same.cpp
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@ -92,4 +92,24 @@ bool ArmTranslatorVisitor::asimd_VORN_reg(bool D, size_t Vn, size_t Vd, bool N,
return true;
}
bool ArmTranslatorVisitor::asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const auto d = ToExtReg(Vd, D);
const auto m = ToExtReg(Vm, M);
const auto n = ToExtReg(Vn, N);
const size_t regs = Q ? 2 : 1;
for (size_t i = 0; i < regs; i++) {
const IR::U32U64 reg_m = ir.GetExtendedRegister(m + i);
const IR::U32U64 reg_n = ir.GetExtendedRegister(n + i);
const IR::U32U64 result = ir.Eor(reg_n, reg_m);
ir.SetExtendedRegister(d + i, result);
}
return true;
}
} // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
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@ -434,6 +434,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VORR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VORN_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Advanced SIMD load/store structures
bool v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);