Lioncash
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7a66224d9a
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A64: Implement EOR3 and BCAX
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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fd8f4c1195
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A64: Implement UCVTF (vector, integer), scalar variant
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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be57608353
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A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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bd2b415850
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A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e97581d063
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fuzz_with_unicorn: Print AArch64 disassembly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5edd623b9d
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b9cd345ddc
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IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f378d2ef1b
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Forward declare IR::Opcode and IR::Type where possible
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e858ce0b35
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A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1d0cd95b23
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A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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afe16fa0f3
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cast_util: Add BitCast and BitCastPointee
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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35a29a9665
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A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1a7b7b541a
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4c5871d5d5
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A64: Implement ADD (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ef906dbbfa
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A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b02b861242
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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c5033b5dda
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A64: Implement CCMN (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8765b421b7
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A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2409e5d082
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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56bc7825ef
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4be55b8b84
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A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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93fcbdf1e2
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A64: Implement FCMP, FCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ed2bedec43
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a5c4fbc783
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A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ab9b5fb8aa
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Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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bafb39ebc5
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A64: Add Disassemble method
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2020-04-22 20:46:12 +01:00 |
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Lioncash
|
7ffbebf290
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A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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98ec9c5f90
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A32: Change UserCallbacks to be similar to A64's interface
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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6fc228f7fd
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ir_opt: Add A64 Get/Set Elimination Pass
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2020-04-22 20:46:12 +01:00 |
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James Rowe
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41e6e659c5
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A64: Implement Load/Store register (unprivileged)
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2020-04-22 20:44:37 +01:00 |
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Lioncash
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5281d3c6d5
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CMakeLists: Add opcodes.inc to the source file list
Allows the file to show up nicely within IDEs
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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30936f5e94
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travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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3caf192f60
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A64: Implement DUP (general)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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db30e02ac8
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emit_x64: Extract BlockRangeInformation, remove template parameter
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2020-04-22 20:44:36 +01:00 |
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MerryMage
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a554e4a329
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backend_x64: Split emit_x64
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2020-04-22 20:42:46 +01:00 |
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Lioncash
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c1a25bfc2f
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A64: Implement MADD and MSUB
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2020-04-22 20:42:46 +01:00 |
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Lioncash
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ae5dbcbed6
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A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
Truly the most difficult A64 instructions to implement.
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2020-04-22 20:42:46 +01:00 |
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Lioncash
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4d8f4aa8af
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A64: Implement ASRV, LSLV, LSRV, and RORV
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2020-04-22 20:42:46 +01:00 |
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MerryMage
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a63fc6c89b
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A64: Implement ADD (vector, vector)
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2020-04-22 20:42:46 +01:00 |
|
Thomas Guillemard
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896cf44f96
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A64: Implement REV, REV32, and REV16 (#126)
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2020-04-22 20:42:46 +01:00 |
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MerryMage
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144b629d8a
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A64: Implement CSEL
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2020-04-22 20:42:45 +01:00 |
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MerryMage
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9f57283a30
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A64: Implement SBFM, BFM, UBFM
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2020-04-22 20:42:45 +01:00 |
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MerryMage
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cdbc8d07a5
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A64: Implement MOVN, MOVZ, MOVK
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2020-04-22 20:42:45 +01:00 |
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MerryMage
|
c6a091d874
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A64: Optimization: Merge interpret blocks
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2020-04-22 20:42:45 +01:00 |
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MerryMage
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b34c6616d4
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A64/decoder: Split decoder data from header
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2020-04-22 20:42:45 +01:00 |
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MerryMage
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72a793f5b0
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ir_opt: Split off A32 specific passes
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
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243f06c613
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A64: Implement LDP, STP
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
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25411da838
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A32: Implement load stores (immediate)
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
68391b0a05
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A64: Implement SVC
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2020-04-22 20:42:45 +01:00 |
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