MerryMage
|
7915f97d98
|
TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)
|
2016-08-06 20:42:06 +01:00 |
|
MerryMage
|
4d127c19dd
|
Common: Add a memory pool implementation, remove use of boost::pool
|
2016-08-06 20:41:00 +01:00 |
|
MerryMage
|
411e804b0d
|
Interface: Forward declare Arm::LocationDescriptor
|
2016-08-06 20:11:35 +01:00 |
|
MerryMage
|
9ab7626374
|
Tests/VFP: Add tests for VADD.F32
|
2016-08-06 20:03:15 +01:00 |
|
MerryMage
|
4b31ea25a7
|
VFP: Implement VADD.{F32,F64}
|
2016-08-06 20:03:15 +01:00 |
|
MerryMage
|
8ff414ee0e
|
Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
|
2016-08-06 20:03:15 +01:00 |
|
MerryMage
|
94d5738f62
|
BackendX64/Routines: Add floating-point constants
|
2016-08-06 20:01:47 +01:00 |
|
MerryMage
|
8754728a82
|
BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case
|
2016-08-06 20:01:47 +01:00 |
|
MerryMage
|
8cc4fe8a10
|
BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly
|
2016-08-06 20:01:47 +01:00 |
|
Merry
|
cd1eef2801
|
Merged in bunnei/dynarmic/load_store (pull request #9)
arm: Implement LDR/LDRB/LDRH/LDRD/STR/STRB/STRH/STRD.
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2016-08-06 14:22:45 +01:00 |
|
bunnei
|
2448d52394
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load_store: Use correct types for LDR/STR.
|
2016-08-05 20:51:32 -04:00 |
|
bunnei
|
8c2300d477
|
arm: Implement LDRD reg/imm instructions.
|
2016-08-05 20:05:02 -04:00 |
|
bunnei
|
72608b7af6
|
arm: Handle Cond::NV (some 3DS games use this despite being obsolete).
|
2016-08-05 20:05:02 -04:00 |
|
bunnei
|
ec3a98cf95
|
arm: Implement LDRH reg/imm instructions.
|
2016-08-05 20:05:01 -04:00 |
|
bunnei
|
192a0fba7a
|
arm: Implement LDRB reg/imm instructions.
|
2016-08-05 20:05:00 -04:00 |
|
bunnei
|
dfb318f208
|
arm: Implement STRD reg/imm instructions.
|
2016-08-05 20:04:59 -04:00 |
|
bunnei
|
e931dc2496
|
arm: Implement STRH reg/imm instructions.
|
2016-08-05 20:04:58 -04:00 |
|
bunnei
|
9f77662b24
|
arm: Implement STRB reg/imm instructions.
|
2016-08-05 20:04:57 -04:00 |
|
bunnei
|
a5e2116e12
|
fuzz_arm: Log write records on failure.
|
2016-08-05 20:04:57 -04:00 |
|
bunnei
|
caab1bbc7c
|
arm: Implement STR reg/imm instructions.
|
2016-08-05 20:04:56 -04:00 |
|
bunnei
|
b09ecb4532
|
arm: Implement LDR reg/imm instructions.
|
2016-08-05 20:04:55 -04:00 |
|
MerryMage
|
856298577d
|
EmitX64: Don't give MOVSX or MOVZX an immediate oparg
|
2016-08-06 01:03:39 +01:00 |
|
MerryMage
|
640ce48baa
|
VFP: Implement {Get,Set}ExtendedRegister{32,64}
|
2016-08-05 19:06:10 +01:00 |
|
MerryMage
|
d31bbd6d14
|
Common/x64/CpuDetect: Disable MSVC warning for strncpy
|
2016-08-05 18:44:01 +01:00 |
|
MerryMage
|
4c0a85f3b3
|
EmitX64: Correct EmitPack2x32To1x64 implementation
|
2016-08-05 18:43:24 +01:00 |
|
MerryMage
|
742eeb8913
|
BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations
|
2016-08-05 18:43:22 +01:00 |
|
MerryMage
|
d2aeb56503
|
Common: DEBUG_ASSERTs weren't enabled
|
2016-08-05 18:43:21 +01:00 |
|
MerryMage
|
6f6f60c61b
|
tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined
|
2016-08-05 16:04:16 +01:00 |
|
MerryMage
|
d80dcc5367
|
BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64
|
2016-08-05 15:27:29 +01:00 |
|
MerryMage
|
2b025183a2
|
BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use
|
2016-08-05 15:24:25 +01:00 |
|
MerryMage
|
b4aa01ccf4
|
Merge remote-tracking branch 'tilkax/master'
|
2016-08-05 14:14:06 +01:00 |
|
MerryMage
|
94e75ad32f
|
BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}
|
2016-08-05 14:11:27 +01:00 |
|
MerryMage
|
92bd5f214b
|
BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg
|
2016-08-05 14:10:39 +01:00 |
|
MerryMage
|
01cfaf0286
|
IR: Properly support Identity in IR::Value
|
2016-08-05 14:09:10 +01:00 |
|
MerryMage
|
ca40015145
|
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
|
2016-08-05 14:07:27 +01:00 |
|
Tillmann Karras
|
fce8c86c90
|
Implement RSB
somehow missed this earlier
|
2016-08-05 02:13:26 +01:00 |
|
Tillmann Karras
|
eb2e6e8bea
|
Implement some multiplies
|
2016-08-05 02:09:54 +01:00 |
|
Tillmann Karras
|
72c503016c
|
Fix Pack2x32To1x64
Not sure how to fix this properly.
|
2016-08-05 02:09:30 +01:00 |
|
Tillmann Karras
|
3fdc093d10
|
Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
|
2016-08-05 02:09:30 +01:00 |
|
Tillmann Karras
|
a97668ead4
|
Simplify ARM fuzz tests
|
2016-08-05 02:09:30 +01:00 |
|
Tillmann Karras
|
023643b4fa
|
Disable load/store tests for now
I don't feel like debugging that right now.
|
2016-08-05 02:09:27 +01:00 |
|
Tillmann Karras
|
ab383b4be5
|
Break tests by fixing them
|
2016-08-05 02:08:41 +01:00 |
|
Tillmann Karras
|
af27ef8d6c
|
Optionally disassemble x86_64 code using LLVM
|
2016-08-05 02:08:41 +01:00 |
|
Merry
|
39563c8ea8
|
Merged in bunnei/dynarmic (pull request #8)
arm: Implement B/BL/BX instructions.
|
2016-08-04 13:22:00 +01:00 |
|
bunnei
|
691e4139fa
|
arm: Implement B/BL/BX instructions.
|
2016-08-03 16:49:01 -04:00 |
|
Tillmann Karras
|
fc33f1d374
|
Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
|
2016-08-03 00:47:17 +01:00 |
|
Tillmann Karras
|
30a90295b9
|
Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
|
2016-08-03 00:47:16 +01:00 |
|
Tillmann Karras
|
fe71cc9d78
|
Disassemble reg-shifted regs in lower case
|
2016-08-03 00:47:16 +01:00 |
|
Tillmann Karras
|
2488926341
|
Add IR opcode RotateRightExtended
to rotate through the carry flag
|
2016-08-03 00:47:16 +01:00 |
|
Tillmann Karras
|
dacaeadb6a
|
Raise SIGTRAP on non-Windows
|
2016-08-03 00:44:08 +01:00 |
|