Merge pull request #584 from lioncash/loads
thumb32: Implement Thumb-2 Load Byte and Memory Hints instructions
This commit is contained in:
merry
GitHub
commit
ea5d8a3047
7 changed files with 275 additions and 18 deletions
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@ -48,6 +48,8 @@ enum class Exception {
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PreloadData,
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/// A PLDW instruction was executed. (Hint instruction.)
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PreloadDataWithIntentToWrite,
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/// A PLI instruction was executed. (Hint instruction.)
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PreloadInstruction,
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};
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/// These function pointers may be inserted into compiled code.
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@ -160,6 +160,9 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
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frontend/A32/translate/impl/thumb32_data_processing_register.cpp
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frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp
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frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
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frontend/A32/translate/impl/thumb32_load_byte.cpp
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frontend/A32/translate/impl/thumb32_load_halfword.cpp
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frontend/A32/translate/impl/thumb32_load_word.cpp
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frontend/A32/translate/impl/thumb32_long_multiply.cpp
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frontend/A32/translate/impl/thumb32_misc.cpp
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frontend/A32/translate/impl/thumb32_multiply.cpp
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@ -146,24 +146,24 @@ INST(thumb32_STRH, "STRH (reg)", "111110000010nnnntttt00
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INST(thumb32_STR_reg, "STR (reg)", "111110000100nnnntttt000000iimmmm")
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// Load Byte and Memory Hints
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//INST(thumb32_PLD_lit, "PLD (lit)", "11111000-00111111111------------")
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//INST(thumb32_PLD_reg, "PLD (reg)", "111110000001----1111000000------")
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//INST(thumb32_PLD_imm8, "PLD (imm8)", "1111100000-1----11111100--------")
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//INST(thumb32_PLD_imm12, "PLD (imm12)", "111110001001----1111------------")
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//INST(thumb32_PLI_lit, "PLI (lit)", "11111001-00111111111------------")
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//INST(thumb32_PLI_reg, "PLI (reg)", "111110010001----1111000000------")
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//INST(thumb32_PLI_imm8, "PLI (imm8)", "111110010001----11111100--------")
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//INST(thumb32_PLI_imm12, "PLI (imm12)", "111110011001----1111------------")
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//INST(thumb32_LDRB_lit, "LDRB (lit)", "11111000-0011111----------------")
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//INST(thumb32_LDRB_reg, "LDRB (reg)", "111110000001--------000000------")
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//INST(thumb32_LDRBT, "LDRBT", "111110000001--------1110--------")
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//INST(thumb32_LDRB_imm8, "LDRB (imm8)", "111110000001--------1-----------")
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//INST(thumb32_LDRB_imm12, "LDRB (imm12)", "111110001001--------------------")
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//INST(thumb32_LDRSB_lit, "LDRSB (lit)", "11111001-0011111----------------")
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//INST(thumb32_LDRSB_reg, "LDRSB (reg)", "111110010001--------000000------")
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//INST(thumb32_LDRSBT, "LDRSBT", "111110010001--------1110--------")
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//INST(thumb32_LDRSB_imm8, "LDRSB (imm8)", "111110010001--------1-----------")
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//INST(thumb32_LDRSB_imm12, "LDRSB (imm12)", "111110011001--------------------")
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INST(thumb32_PLD_lit, "PLD (lit)", "11111000U00111111111iiiiiiiiiiii")
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INST(thumb32_PLD_reg, "PLD (reg)", "1111100000W1nnnn1111000000iimmmm")
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INST(thumb32_PLD_imm8, "PLD (imm8)", "1111100000W1nnnn11111100iiiiiiii")
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INST(thumb32_PLD_imm12, "PLD (imm12)", "1111100010W1nnnn1111iiiiiiiiiiii")
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INST(thumb32_PLI_lit, "PLI (lit)", "11111001U00111111111iiiiiiiiiiii")
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INST(thumb32_PLI_reg, "PLI (reg)", "111110010001nnnn1111000000iimmmm")
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INST(thumb32_PLI_imm8, "PLI (imm8)", "111110010001nnnn11111100iiiiiiii")
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INST(thumb32_PLI_imm12, "PLI (imm12)", "111110011001nnnn1111iiiiiiiiiiii")
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INST(thumb32_LDRB_lit, "LDRB (lit)", "11111000U0011111ttttiiiiiiiiiiii")
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INST(thumb32_LDRB_reg, "LDRB (reg)", "111110000001nnnntttt000000iimmmm")
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INST(thumb32_LDRBT, "LDRBT", "111110000001nnnntttt1110iiiiiiii")
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INST(thumb32_LDRB_imm8, "LDRB (imm8)", "111110000001nnnntttt1PUWiiiiiiii")
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INST(thumb32_LDRB_imm12, "LDRB (imm12)", "111110001001nnnnttttiiiiiiiiiiii")
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INST(thumb32_LDRSB_lit, "LDRSB (lit)", "11111001U0011111ttttiiiiiiiiiiii")
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INST(thumb32_LDRSB_reg, "LDRSB (reg)", "111110010001nnnntttt000000iimmmm")
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INST(thumb32_LDRSBT, "LDRSBT", "111110010001nnnntttt1110iiiiiiii")
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INST(thumb32_LDRSB_imm8, "LDRSB (imm8)", "111110010001nnnntttt1PUWiiiiiiii")
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INST(thumb32_LDRSB_imm12, "LDRSB (imm12)", "111110011001nnnnttttiiiiiiiiiiii")
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// Load Halfword and Memory Hints
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//INST(thumb32_LDRH_lit, "LDRH (lit)", "11111000-0111111----------------")
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210
src/frontend/A32/translate/impl/thumb32_load_byte.cpp
Normal file
210
src/frontend/A32/translate/impl/thumb32_load_byte.cpp
Normal file
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@ -0,0 +1,210 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2021 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include <dynarmic/A32/config.h>
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#include "frontend/A32/translate/impl/translate_thumb.h"
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namespace Dynarmic::A32 {
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static bool PLDHandler(ThumbTranslatorVisitor& v, bool W) {
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if (!v.options.hook_hint_instructions) {
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return true;
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}
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const auto exception = W ? Exception::PreloadDataWithIntentToWrite
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: Exception::PreloadData;
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return v.RaiseException(exception);
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}
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static bool PLIHandler(ThumbTranslatorVisitor& v) {
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if (!v.options.hook_hint_instructions) {
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return true;
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}
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return v.RaiseException(Exception::PreloadInstruction);
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}
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using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U8&);
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static bool LoadByteLiteral(ThumbTranslatorVisitor& v, bool U, Reg t, Imm<12> imm12,
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ExtensionFunction ext_fn) {
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const u32 imm32 = imm12.ZeroExtend();
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const u32 base = v.ir.AlignPC(4);
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const u32 address = U ? (base + imm32) : (base - imm32);
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const auto data = (v.ir.*ext_fn)(v.ir.ReadMemory8(v.ir.Imm32(address)));
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v.ir.SetRegister(t, data);
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return true;
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}
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static bool LoadByteRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m,
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ExtensionFunction ext_fn) {
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if (m == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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const auto reg_n = v.ir.GetRegister(n);
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const auto reg_m = v.ir.GetRegister(m);
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const auto offset = v.ir.LogicalShiftLeft(reg_m, v.ir.Imm8(imm2.ZeroExtend<u8>()));
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const auto address = v.ir.Add(reg_n, offset);
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const auto data = (v.ir.*ext_fn)(v.ir.ReadMemory8(address));
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v.ir.SetRegister(t, data);
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return true;
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}
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static bool LoadByteImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W,
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Imm<12> imm12, ExtensionFunction ext_fn) {
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const u32 imm32 = imm12.ZeroExtend();
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm32));
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const IR::U32 address = P ? offset_address : reg_n;
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const IR::U32 data = (v.ir.*ext_fn)(v.ir.ReadMemory8(address));
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v.ir.SetRegister(t, data);
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_PLD_lit([[maybe_unused]] bool U,
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[[maybe_unused]] Imm<12> imm12) {
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return PLDHandler(*this, false);
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}
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bool ThumbTranslatorVisitor::thumb32_PLD_imm8(bool W,
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[[maybe_unused]] Reg n,
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[[maybe_unused]] Imm<8> imm8) {
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return PLDHandler(*this, W);
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}
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bool ThumbTranslatorVisitor::thumb32_PLD_imm12(bool W,
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[[maybe_unused]] Reg n,
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[[maybe_unused]] Imm<12> imm12) {
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return PLDHandler(*this, W);
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}
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bool ThumbTranslatorVisitor::thumb32_PLD_reg(bool W,
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[[maybe_unused]] Reg n,
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[[maybe_unused]] Imm<2> imm2,
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Reg m) {
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if (m == Reg::PC) {
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return UnpredictableInstruction();
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}
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return PLDHandler(*this, W);
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}
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bool ThumbTranslatorVisitor::thumb32_PLI_lit([[maybe_unused]] bool U,
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[[maybe_unused]] Imm<12> imm12) {
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return PLIHandler(*this);
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}
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bool ThumbTranslatorVisitor::thumb32_PLI_imm8([[maybe_unused]] Reg n,
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[[maybe_unused]] Imm<8> imm8) {
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return PLIHandler(*this);
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}
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bool ThumbTranslatorVisitor::thumb32_PLI_imm12([[maybe_unused]] Reg n,
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[[maybe_unused]] Imm<12> imm12) {
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return PLIHandler(*this);
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}
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bool ThumbTranslatorVisitor::thumb32_PLI_reg([[maybe_unused]] Reg n,
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[[maybe_unused]] Imm<2> imm2,
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Reg m) {
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if (m == Reg::PC) {
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return UnpredictableInstruction();
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}
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return PLIHandler(*this);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRB_lit(bool U, Reg t, Imm<12> imm12) {
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return LoadByteLiteral(*this, U, t, imm12, &IREmitter::ZeroExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
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if (t == Reg::PC && W) {
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return UnpredictableInstruction();
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}
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if (W && n == t) {
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return UnpredictableInstruction();
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}
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if (!P && !W) {
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return UndefinedInstruction();
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}
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return LoadByteImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
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&IREmitter::ZeroExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12) {
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return LoadByteImmediate(*this, n, t, true, true, false, imm12,
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&IREmitter::ZeroExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRB_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
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return LoadByteRegister(*this, n, t, imm2, m, &IREmitter::ZeroExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8) {
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// TODO: Add an unpredictable instruction path if this
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// is executed in hypervisor mode if we ever support
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// privileged execution modes.
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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// Treat it as a normal LDRB, given we don't support
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// execution levels other than EL0 currently.
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return thumb32_LDRB_imm8(n, t, true, true, false, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSB_lit(bool U, Reg t, Imm<12> imm12) {
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return LoadByteLiteral(*this, U, t, imm12, &IREmitter::SignExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
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if (t == Reg::PC && W) {
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return UnpredictableInstruction();
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}
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if (W && n == t) {
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return UnpredictableInstruction();
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}
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if (!P && !W) {
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return UndefinedInstruction();
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}
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return LoadByteImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
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&IREmitter::SignExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12) {
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return LoadByteImmediate(*this, n, t, true, true, false, imm12,
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&IREmitter::SignExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSB_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
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return LoadByteRegister(*this, n, t, imm2, m, &IREmitter::SignExtendByteToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8) {
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// TODO: Add an unpredictable instruction path if this
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// is executed in hypervisor mode if we ever support
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// privileged execution modes.
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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// Treat it as a normal LDRSB, given we don't support
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// execution levels other than EL0 currently.
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return thumb32_LDRSB_imm8(n, t, true, true, false, imm8);
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}
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} // namespace Dynarmic::A32
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11
src/frontend/A32/translate/impl/thumb32_load_halfword.cpp
Normal file
11
src/frontend/A32/translate/impl/thumb32_load_halfword.cpp
Normal file
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@ -0,0 +1,11 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2021 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "frontend/A32/translate/impl/translate_thumb.h"
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namespace Dynarmic::A32 {
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} // namespace Dynarmic::A32
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11
src/frontend/A32/translate/impl/thumb32_load_word.cpp
Normal file
11
src/frontend/A32/translate/impl/thumb32_load_word.cpp
Normal file
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@ -0,0 +1,11 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2021 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "frontend/A32/translate/impl/translate_thumb.h"
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namespace Dynarmic::A32 {
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} // namespace Dynarmic::A32
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@ -207,6 +207,26 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m);
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bool thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
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// thumb32 load byte and memory hints
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bool thumb32_PLD_lit(bool U, Imm<12> imm12);
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bool thumb32_PLD_imm8(bool W, Reg n, Imm<8> imm8);
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bool thumb32_PLD_imm12(bool W, Reg n, Imm<12> imm12);
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bool thumb32_PLD_reg(bool W, Reg n, Imm<2> imm2, Reg m);
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bool thumb32_PLI_lit(bool U, Imm<12> imm12);
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bool thumb32_PLI_imm8(Reg n, Imm<8> imm8);
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bool thumb32_PLI_imm12(Reg n, Imm<12> imm12);
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bool thumb32_PLI_reg(Reg n, Imm<2> imm2, Reg m);
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bool thumb32_LDRB_lit(bool U, Reg t, Imm<12> imm12);
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bool thumb32_LDRB_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
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bool thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
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bool thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_LDRSB_lit(bool U, Reg t, Imm<12> imm12);
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bool thumb32_LDRSB_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
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bool thumb32_LDRSB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
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bool thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8);
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// thumb32 data processing (register) instructions
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bool thumb32_ASR_reg(Reg m, Reg d, Reg s);
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bool thumb32_LSL_reg(Reg m, Reg d, Reg s);
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