thumb32: Implement B (T3)

This commit is contained in:
MerryMage 2021-03-06 17:28:19 +00:00
parent 86aa3f0701
commit 531bb42ab5
3 changed files with 20 additions and 1 deletions

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@ -125,7 +125,8 @@ INST(thumb32_UDF, "UDF", "111101111111----1010--
INST(thumb32_BL_imm, "BL (imm)", "11110Svvvvvvvvvv11j1jvvvvvvvvvvv") // v4T
INST(thumb32_BLX_imm, "BLX (imm)", "11110Svvvvvvvvvv11j0jvvvvvvvvvvv") // v5T
INST(thumb32_B, "B", "11110Svvvvvvvvvv10j1jvvvvvvvvvvv")
//INST(thumb32_B_cond, "B (cond)", "11110-----------10-0------------")
INST(thumb32_UDF, "Invalid decoding", "11110-111-------10-0------------")
INST(thumb32_B_cond, "B (cond)", "11110Sccccvvvvvv10i0ivvvvvvvvvvv")
// Store Single Data Item
//INST(thumb32_STRB_imm_1, "STRB (imm)", "111110000000--------1--1--------")

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@ -68,4 +68,21 @@ bool ThumbTranslatorVisitor::thumb32_B(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j
return false;
}
bool ThumbTranslatorVisitor::thumb32_B_cond(Imm<1> S, Cond cond, Imm<6> hi, Imm<1> i1, Imm<1> i2, Imm<11> lo) {
if (ir.current_location.IT().IsInITBlock()) {
return UnpredictableInstruction();
}
// Note: i1 and i2 were not inverted from encoding and are opposite compared to the other B instructions.
const s32 imm32 = static_cast<s32>((concatenate(S, i2, i1, hi, lo).SignExtend<u32>() << 1) + 4);
const auto then_location = ir.current_location
.AdvancePC(imm32)
.AdvanceIT();
const auto else_location = ir.current_location
.AdvancePC(4)
.AdvanceIT();
ir.SetTerm(IR::Term::If{cond, IR::Term::LinkBlock{then_location}, IR::Term::LinkBlock{else_location}});
return false;
}
} // namespace Dynarmic::A32

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@ -200,6 +200,7 @@ struct ThumbTranslatorVisitor final {
bool thumb32_BL_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo);
bool thumb32_BLX_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo);
bool thumb32_B(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo);
bool thumb32_B_cond(Imm<1> S, Cond cond, Imm<6> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo);
// thumb32 store single data item instructions
bool thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m);