Tillmann Karras
|
3fdc093d10
|
Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
|
2016-08-05 02:09:30 +01:00 |
|
Tillmann Karras
|
af27ef8d6c
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Optionally disassemble x86_64 code using LLVM
|
2016-08-05 02:08:41 +01:00 |
|
Tillmann Karras
|
2488926341
|
Add IR opcode RotateRightExtended
to rotate through the carry flag
|
2016-08-03 00:47:16 +01:00 |
|
Tillmann Karras
|
306e070ab5
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Use opcodes.inc for emit_x64.h
|
2016-08-03 00:44:08 +01:00 |
|
MerryMage
|
1252bd653d
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RegAlloc: Define constructors for HostLocInfo to make MSVC happy
|
2016-08-03 00:25:42 +01:00 |
|
MerryMage
|
4414ec5bc8
|
RegAlloc: Allow allocation of XMM registers
|
2016-08-02 13:46:12 +01:00 |
|
MerryMage
|
864081d1a0
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BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR
|
2016-08-02 12:00:11 +01:00 |
|
MerryMage
|
93af160c97
|
arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
|
2016-08-02 11:54:02 +01:00 |
|
MerryMage
|
be87038ffd
|
IROpt: Port get/set elimination pass to current IR
|
2016-08-02 11:51:05 +01:00 |
|
MerryMage
|
51448aa06d
|
More Speed
|
2016-07-22 23:55:00 +01:00 |
|
MerryMage
|
5fbfc6c155
|
Implement some simple IR optimizations (get/set eliminiation and DCE)
|
2016-07-21 21:48:45 +01:00 |
|
MerryMage
|
90d317b868
|
Implement memory endianness. Implement Thumb SETEND instruction.
|
2016-07-20 15:34:17 +01:00 |
|
MerryMage
|
3f11a149d7
|
Implement Thumb Instructions: BLX (imm), BL (imm)
|
2016-07-18 22:18:58 +01:00 |
|
MerryMage
|
e0d6e28b67
|
Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
|
2016-07-18 21:04:39 +01:00 |
|
MerryMage
|
8a310777a1
|
backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
|
2016-07-18 20:01:48 +01:00 |
|
Subv
|
703a46ec99
|
Pass the current IR::Block by reference to the emitter.
This avoids calling the copy constructor more times than needed.
|
2016-07-18 11:27:33 -05:00 |
|
MerryMage
|
f7e3d7b8d2
|
Implement Thumb PUSH instruction
|
2016-07-18 15:11:16 +01:00 |
|
MerryMage
|
c18a3eeab4
|
Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
|
2016-07-18 10:38:22 +01:00 |
|
MerryMage
|
3720da4e19
|
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
|
2016-07-16 19:23:42 +01:00 |
|
MerryMage
|
07eaf100ba
|
Reorganise src/frontend: Add subdirectories disassembler and translate
|
2016-07-14 14:39:43 +01:00 |
|
MerryMage
|
9b2aff166a
|
Implement arm_SVC
|
2016-07-14 14:29:46 +01:00 |
|
MerryMage
|
7d7751c157
|
Allow IR blocks to require a cond for block entry.
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
|
2016-07-14 12:52:53 +01:00 |
|
MerryMage
|
4ab4ca58f9
|
backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight
|
2016-07-14 09:02:27 +01:00 |
|
MerryMage
|
08e848044d
|
backend_x64: Inline Routines::GenReturnFromRunCode into emitted code
|
2016-07-12 16:46:27 +01:00 |
|
MerryMage
|
619b451902
|
clang support
|
2016-07-12 14:31:43 +01:00 |
|
MerryMage
|
8449deb0bc
|
MSVC support
|
2016-07-12 13:28:09 +01:00 |
|
MerryMage
|
09420d190b
|
IR: Implement IR microinstructions ALUWritePC and LoadWritePC
|
2016-07-12 10:58:14 +01:00 |
|
MerryMage
|
1410221b47
|
Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
|
2016-07-11 23:11:05 +01:00 |
|
MerryMage
|
e7922e4fef
|
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
|
2016-07-11 22:43:53 +01:00 |
|
MerryMage
|
cbcf61a9e6
|
backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI
|
2016-07-11 15:28:10 +01:00 |
|
MerryMage
|
d11df9067d
|
Implement thumb1_BIC_reg
|
2016-07-10 10:44:45 +08:00 |
|
MerryMage
|
98a64a92b1
|
Implement thumb1_ORR_reg
|
2016-07-10 09:06:38 +08:00 |
|
MerryMage
|
8145b33882
|
Implemented thumb1_ROR_reg
|
2016-07-10 08:18:17 +08:00 |
|
MerryMage
|
aa72323823
|
Implement thumb1_CMP_imm
|
2016-07-08 21:32:01 +08:00 |
|
MerryMage
|
92142d5a22
|
Implement thumb1_SUB_reg
|
2016-07-08 18:49:30 +08:00 |
|
MerryMage
|
df0c324923
|
Implement thumb1_EOR_reg
|
2016-07-08 18:14:54 +08:00 |
|
MerryMage
|
8a0511d297
|
Implement thumb1_AND_reg
|
2016-07-08 17:44:53 +08:00 |
|
MerryMage
|
d0b48bfb59
|
Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
|
2016-07-08 17:44:51 +08:00 |
|
MerryMage
|
e93fb0ba2b
|
EmitX64: remove emit_fns map, use a switch statement instead
|
2016-07-08 15:28:56 +08:00 |
|
MerryMage
|
421ab344ad
|
EmitX64::EmitTerminalInterpret: Restore RSP before CALL
|
2016-07-07 22:03:45 +08:00 |
|
MerryMage
|
e5f6450a24
|
Start implementing Thumb disassembler
|
2016-07-07 21:51:47 +08:00 |
|
MerryMage
|
f31b530703
|
Fuzz thumb instructions
|
2016-07-07 19:01:47 +08:00 |
|
MerryMage
|
5711e62419
|
Implement terminal instructions
|
2016-07-07 17:53:09 +08:00 |
|
MerryMage
|
14388ea690
|
Proper implementation of Arm::Translate
|
2016-07-04 21:37:50 +08:00 |
|
MerryMage
|
d743adf518
|
Reorganisation, Import Skyeye, This is a mess
|
2016-07-04 17:22:11 +08:00 |
|
MerryMage
|
65df15633d
|
First Commit
|
2016-07-01 21:01:06 +08:00 |
|