Tillmann Karras
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846d07d7b5
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Add Sub64 opcode
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2016-08-06 21:17:11 +01:00 |
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Tillmann Karras
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b9f4f1ed0f
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Add carry support to MostSignificantWord
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2016-08-06 21:17:11 +01:00 |
|
Tillmann Karras
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01aebcb385
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Remove *MulHi wrappers
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2016-08-06 21:17:11 +01:00 |
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MerryMage
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4d127c19dd
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Common: Add a memory pool implementation, remove use of boost::pool
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2016-08-06 20:41:00 +01:00 |
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MerryMage
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4b31ea25a7
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VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
|
MerryMage
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640ce48baa
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VFP: Implement {Get,Set}ExtendedRegister{32,64}
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2016-08-05 19:06:10 +01:00 |
|
MerryMage
|
b4aa01ccf4
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Merge remote-tracking branch 'tilkax/master'
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2016-08-05 14:14:06 +01:00 |
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MerryMage
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01cfaf0286
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IR: Properly support Identity in IR::Value
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2016-08-05 14:09:10 +01:00 |
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MerryMage
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ca40015145
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IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
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2016-08-05 14:07:27 +01:00 |
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Tillmann Karras
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3fdc093d10
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Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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2488926341
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Add IR opcode RotateRightExtended
to rotate through the carry flag
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2016-08-03 00:47:16 +01:00 |
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MerryMage
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deb5e2c10d
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IR::DumpBlock: Incorrect use of std::map::at
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2016-08-02 13:47:05 +01:00 |
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MerryMage
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4414ec5bc8
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RegAlloc: Allow allocation of XMM registers
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2016-08-02 13:46:12 +01:00 |
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MerryMage
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93af160c97
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arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
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2016-08-02 11:54:02 +01:00 |
|
MerryMage
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be87038ffd
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IROpt: Port get/set elimination pass to current IR
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2016-08-02 11:51:05 +01:00 |
|
MerryMage
|
51448aa06d
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More Speed
|
2016-07-22 23:55:00 +01:00 |
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MerryMage
|
5fbfc6c155
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Implement some simple IR optimizations (get/set eliminiation and DCE)
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2016-07-21 21:48:45 +01:00 |
|
MerryMage
|
90d317b868
|
Implement memory endianness. Implement Thumb SETEND instruction.
|
2016-07-20 15:34:17 +01:00 |
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MerryMage
|
e0d6e28b67
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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
|
2016-07-18 21:04:39 +01:00 |
|
MerryMage
|
f7e3d7b8d2
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Implement Thumb PUSH instruction
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2016-07-18 15:11:16 +01:00 |
|
MerryMage
|
c18a3eeab4
|
Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
|
2016-07-18 10:38:22 +01:00 |
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MerryMage
|
3720da4e19
|
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
|
2016-07-16 19:23:42 +01:00 |
|
MerryMage
|
07eaf100ba
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Reorganise src/frontend: Add subdirectories disassembler and translate
|
2016-07-14 14:39:43 +01:00 |
|
MerryMage
|
9b2aff166a
|
Implement arm_SVC
|
2016-07-14 14:29:46 +01:00 |
|
MerryMage
|
7d7751c157
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Allow IR blocks to require a cond for block entry.
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
|
2016-07-14 12:52:53 +01:00 |
|
MerryMage
|
09420d190b
|
IR: Implement IR microinstructions ALUWritePC and LoadWritePC
|
2016-07-12 10:58:14 +01:00 |
|
MerryMage
|
1410221b47
|
Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
|
2016-07-11 23:11:05 +01:00 |
|
MerryMage
|
e7922e4fef
|
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
|
2016-07-11 22:43:53 +01:00 |
|
MerryMage
|
d11df9067d
|
Implement thumb1_BIC_reg
|
2016-07-10 10:44:45 +08:00 |
|
MerryMage
|
98a64a92b1
|
Implement thumb1_ORR_reg
|
2016-07-10 09:06:38 +08:00 |
|
MerryMage
|
8145b33882
|
Implemented thumb1_ROR_reg
|
2016-07-10 08:18:17 +08:00 |
|
MerryMage
|
92142d5a22
|
Implement thumb1_SUB_reg
|
2016-07-08 18:49:30 +08:00 |
|
MerryMage
|
df0c324923
|
Implement thumb1_EOR_reg
|
2016-07-08 18:14:54 +08:00 |
|
MerryMage
|
8a0511d297
|
Implement thumb1_AND_reg
|
2016-07-08 17:44:53 +08:00 |
|
MerryMage
|
d0b48bfb59
|
Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
|
2016-07-08 17:44:51 +08:00 |
|
MerryMage
|
5711e62419
|
Implement terminal instructions
|
2016-07-07 17:53:09 +08:00 |
|
MerryMage
|
14388ea690
|
Proper implementation of Arm::Translate
|
2016-07-04 21:37:50 +08:00 |
|
MerryMage
|
d743adf518
|
Reorganisation, Import Skyeye, This is a mess
|
2016-07-04 17:22:11 +08:00 |
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