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371 commits

Author SHA1 Message Date
Lioncash
eba3a06d80 frontend: Introduce FPSCR register helper class 
Encapsulates all of the FPSCR state.
 2016-08-24 20:51:14 +01:00
MerryMage
b5a86889cd Implement VCVT 2016-08-23 22:20:04 +01:00
Lioncash
d5805cc6eb intrusive_list: Add size querying 
Since we store pointers and have an interface for iterators
set up, the count is just the distance from the beginning
to the end of the list.

Nice thing is that because of this, basic blocks also get
the ability to have a size count without needing to do anything
directly.
 2016-08-23 19:52:09 +01:00
Lioncash
2180a4be7a basic_block: Use a range-based for loop for iteration 2016-08-23 19:51:01 +01:00
MerryMage
e0f9dead5d microinstruction: Identity's type depends on the type of its argument 2016-08-23 15:48:30 +01:00
MerryMage
8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
Lioncash
47f285249b microinstruction: Introduce convenience informational functions 
Whenever more rigorous optimizations are attempted (or even basic ones),
it's usually helpful to know what overall kind of instruction is being
dealt with, in the event certain classes of instructions may be eligible
for optimization.
 2016-08-22 21:36:48 +01:00
Lioncash
06ec4b5977 microinstruction: Make constructor explicit 2016-08-22 16:01:18 +01:00
Lioncash
1abe881921 basic_block: Add proxy member functions for the instruction list 
Currently basic block kind of acts like a 'dumb struct' which makes things
a little more verbose to write (as opposed to keeping it all in one place,
I guess). It's also a little wonky conceptually, considering a block is
composed of instructions (i.e. 'contains' them).

So providing accessors that make it act more like a container can make working
with algorithms a little nicer. It also makes the API a little more
defined.

Ideally, the list would be only available through a function, but
currently, the pool allocator is exposed, which seems somewhat odd,
considering the block itself should manage its overall allocations
(with placement new, and regular new), rather than putting that
sanitizing directly on the IR emitter (it should just care about emission,
not block state). However, recontaining that can be followed up with,
as it's very trivial to do.
 2016-08-22 13:44:56 +01:00
Lioncash
23d190f7b0 intrusive_list: Support inserters 
Allows std::inserter, std::back_inserter, and std::front_inserter to work
with intrusive lists.
 2016-08-19 20:25:17 +01:00
MerryMage
192a0029be ir/opcodes: Implement IR::AreTypesCompatible 
Type-checking is now occuring in more than one place.
 2016-08-19 01:34:14 +01:00
Tillmann Karras
9782e7da3f verification_pass: show type errors 2016-08-19 01:17:30 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
MerryMage
7d7ac0af71 Optimization: Make SVC use RSB 2016-08-15 15:02:08 +01:00
MerryMage
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
MerryMage
960d14d18e Optimization: Implement Return Stack Buffer 2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
MerryMage
8964b38cf9 IR/DumpBlock: Print references to ExtRegs 2016-08-11 17:15:02 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
2eec43178a IR: Opaque can be of any type 2016-08-09 22:46:44 +01:00
Tillmann Karras
5d26899ac9 Add simplified LogicalShiftRight64 IR opcode 2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5 Add support for the APSR.Q flag 2016-08-08 22:27:04 +01:00
MerryMage
a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage
0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage
3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage
94b99f5949 Common: Add an intrusive list implementation; remove use of boost::intrusive::list. 2016-08-06 22:23:01 +01:00
Tillmann Karras
846d07d7b5 Add Sub64 opcode 2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
Tillmann Karras
01aebcb385 Remove *MulHi wrappers 2016-08-06 21:17:11 +01:00
MerryMage
4d127c19dd Common: Add a memory pool implementation, remove use of boost::pool 2016-08-06 20:41:00 +01:00
MerryMage
4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage
640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} 2016-08-05 19:06:10 +01:00
MerryMage
b4aa01ccf4 Merge remote-tracking branch 'tilkax/master' 2016-08-05 14:14:06 +01:00
MerryMage
01cfaf0286 IR: Properly support Identity in IR::Value 2016-08-05 14:09:10 +01:00
MerryMage
ca40015145 IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint) 2016-08-05 14:07:27 +01:00
Tillmann Karras
3fdc093d10 Add more IR opcodes for multiply instructions 
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
 2016-08-05 02:09:30 +01:00
Tillmann Karras
2488926341 Add IR opcode RotateRightExtended 
to rotate through the carry flag
 2016-08-03 00:47:16 +01:00
MerryMage
deb5e2c10d IR::DumpBlock: Incorrect use of std::map::at 2016-08-02 13:47:05 +01:00
MerryMage
4414ec5bc8 RegAlloc: Allow allocation of XMM registers 2016-08-02 13:46:12 +01:00
MerryMage
93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage
be87038ffd IROpt: Port get/set elimination pass to current IR 2016-08-02 11:51:05 +01:00
MerryMage
51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage
5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage
90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage
e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
MerryMage
f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage
c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage
3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage
07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage
9b2aff166a Implement arm_SVC 2016-07-14 14:29:46 +01:00
MerryMage
7d7751c157 Allow IR blocks to require a cond for block entry. 
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
 2016-07-14 12:52:53 +01:00
MerryMage
09420d190b IR: Implement IR microinstructions ALUWritePC and LoadWritePC 2016-07-12 10:58:14 +01:00
MerryMage
1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage
e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage
d11df9067d Implement thumb1_BIC_reg 2016-07-10 10:44:45 +08:00
MerryMage
98a64a92b1 Implement thumb1_ORR_reg 2016-07-10 09:06:38 +08:00
MerryMage
8145b33882 Implemented thumb1_ROR_reg 2016-07-10 08:18:17 +08:00
MerryMage
92142d5a22 Implement thumb1_SUB_reg 2016-07-08 18:49:30 +08:00
MerryMage
df0c324923 Implement thumb1_EOR_reg 2016-07-08 18:14:54 +08:00
MerryMage
8a0511d297 Implement thumb1_AND_reg 2016-07-08 17:44:53 +08:00
MerryMage
d0b48bfb59 Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2 2016-07-08 17:44:51 +08:00
MerryMage
5711e62419 Implement terminal instructions 2016-07-07 17:53:09 +08:00
MerryMage
14388ea690 Proper implementation of Arm::Translate 2016-07-04 21:37:50 +08:00
MerryMage
d743adf518 Reorganisation, Import Skyeye, This is a mess 2016-07-04 17:22:11 +08:00