MerryMage
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92bd5f214b
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BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg
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2016-08-05 14:10:39 +01:00 |
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MerryMage
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01cfaf0286
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IR: Properly support Identity in IR::Value
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2016-08-05 14:09:10 +01:00 |
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MerryMage
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ca40015145
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IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
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2016-08-05 14:07:27 +01:00 |
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Merry
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39563c8ea8
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Merged in bunnei/dynarmic (pull request #8)
arm: Implement B/BL/BX instructions.
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2016-08-04 13:22:00 +01:00 |
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bunnei
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691e4139fa
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arm: Implement B/BL/BX instructions.
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2016-08-03 16:49:01 -04:00 |
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Tillmann Karras
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fc33f1d374
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Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
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2016-08-03 00:47:17 +01:00 |
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Tillmann Karras
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30a90295b9
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Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
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2016-08-03 00:47:16 +01:00 |
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Tillmann Karras
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fe71cc9d78
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Disassemble reg-shifted regs in lower case
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2016-08-03 00:47:16 +01:00 |
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Tillmann Karras
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2488926341
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Add IR opcode RotateRightExtended
to rotate through the carry flag
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2016-08-03 00:47:16 +01:00 |
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Tillmann Karras
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dacaeadb6a
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Raise SIGTRAP on non-Windows
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2016-08-03 00:44:08 +01:00 |
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Tillmann Karras
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306e070ab5
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Use opcodes.inc for emit_x64.h
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2016-08-03 00:44:08 +01:00 |
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Tillmann Karras
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61eddbd1fa
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Fix Linux build
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2016-08-03 00:44:08 +01:00 |
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MerryMage
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1252bd653d
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RegAlloc: Define constructors for HostLocInfo to make MSVC happy
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2016-08-03 00:25:42 +01:00 |
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MerryMage
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a875c0c720
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TranslateArm: Stub more ARM instructions
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2016-08-02 21:59:33 +01:00 |
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MerryMage
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64c17a2489
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tests/FuzzArm: Print out IR upon failure
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2016-08-02 13:48:06 +01:00 |
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MerryMage
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deb5e2c10d
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IR::DumpBlock: Incorrect use of std::map::at
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2016-08-02 13:47:05 +01:00 |
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MerryMage
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4414ec5bc8
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RegAlloc: Allow allocation of XMM registers
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2016-08-02 13:46:12 +01:00 |
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MerryMage
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864081d1a0
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BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR
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2016-08-02 12:00:11 +01:00 |
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MerryMage
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6097a21955
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TranslateArm: Reorganisation - Split visitor into multiple .cpp files
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2016-08-02 11:54:04 +01:00 |
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MerryMage
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93af160c97
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arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
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2016-08-02 11:54:02 +01:00 |
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MerryMage
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be87038ffd
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IROpt: Port get/set elimination pass to current IR
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2016-08-02 11:51:05 +01:00 |
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MerryMage
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e60cea3a54
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Add -pedantic-errors compilation flag
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2016-08-01 19:54:31 +01:00 |
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MerryMage
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cd86ef4236
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Add -DBOOST_POOL_NO_MT as a compiler flag
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2016-07-23 05:37:07 +01:00 |
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MerryMage
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51448aa06d
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More Speed
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2016-07-22 23:55:00 +01:00 |
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MerryMage
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5fbfc6c155
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Implement some simple IR optimizations (get/set eliminiation and DCE)
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2016-07-21 21:48:45 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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MerryMage
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98bd7ff6a5
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Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support.
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2016-07-20 12:08:17 +01:00 |
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Merry
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95316b8443
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Merged in Subv/dynarmic/arm_mem_tests (pull request #4)
Added some fuzz tests for most cases of ARM Load/Store instructions
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2016-07-20 10:19:55 +01:00 |
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MerryMage
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95588d3faa
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Fix Thumb BLX (imm), BL (imm) for negative immediates
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2016-07-18 22:48:23 +01:00 |
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MerryMage
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3f11a149d7
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Implement Thumb Instructions: BLX (imm), BL (imm)
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2016-07-18 22:18:58 +01:00 |
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Subv
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fce8f75077
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Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC.
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2016-07-18 16:13:33 -05:00 |
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Subv
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426ffc9971
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Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH.
These tests do not test the behavior of writing to the PC.
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2016-07-18 16:13:02 -05:00 |
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Subv
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c330d9e0e3
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Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests.
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2016-07-18 16:10:35 -05:00 |
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MerryMage
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e0d6e28b67
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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
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2016-07-18 21:04:39 +01:00 |
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Subv
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ccc61472b9
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Added format strings for ARM STRBT encodings A1 and A2
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2016-07-18 14:20:58 -05:00 |
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Subv
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8617bf80a1
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Added format strings for ARM LDRBT encodings A1 and A2
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2016-07-18 14:18:39 -05:00 |
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Subv
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5d5ea9325c
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Added format strings for ARM STRT encodings A1 and A2
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2016-07-18 14:05:53 -05:00 |
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MerryMage
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2363759c62
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Implement thumb STM, LDM. Fix thumb POP implementation for P=1.
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2016-07-18 20:05:35 +01:00 |
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MerryMage
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8a310777a1
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backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
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2016-07-18 20:01:48 +01:00 |
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Subv
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77761ba032
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Added the format strings for LDRT encodings A1 and A2.
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2016-07-18 14:01:18 -05:00 |
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MerryMage
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14dcb18bbe
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Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)
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2016-07-18 18:48:08 +01:00 |
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MerryMage
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a605a43ef9
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Implement Thumb Instructions: STRH (imm), LDRH (imm)
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2016-07-18 18:28:52 +01:00 |
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MerryMage
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f9755870bb
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Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)
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2016-07-18 18:02:02 +01:00 |
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Merry
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3b8790bf29
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Merged in Subv/dynarmic/small_opt (pull request #3)
Pass the current IR::Block by reference to the emitter.
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2016-07-18 17:38:12 +01:00 |
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MerryMage
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dfef65d98f
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Implement thumb POP instruction
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2016-07-18 17:37:48 +01:00 |
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Subv
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703a46ec99
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Pass the current IR::Block by reference to the emitter.
This avoids calling the copy constructor more times than needed.
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2016-07-18 11:27:33 -05:00 |
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MerryMage
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f7e3d7b8d2
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Implement Thumb PUSH instruction
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2016-07-18 15:11:16 +01:00 |
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MerryMage
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9109b226af
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Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)
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2016-07-18 11:16:12 +01:00 |
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MerryMage
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c18a3eeab4
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Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
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2016-07-18 10:38:22 +01:00 |
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MerryMage
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bf99ddd065
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Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic
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2016-07-18 10:33:52 +01:00 |
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