MerryMage
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4f6ea715b2
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emit_x64: EmitX64::Emit doesn't need descriptor argument
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2016-08-26 19:14:25 +01:00 |
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MerryMage
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ed3a686d1d
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Implement public header files
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2016-08-26 00:44:50 +01:00 |
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MerryMage
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656d4f7252
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emit_x64: inhibit_emission is obsolete
Not used anymore; unused ever since intrusive lists were introduced.
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2016-08-25 23:24:16 +01:00 |
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MerryMage
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e32812cd00
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Port x64 backend to xbyak
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2016-08-25 16:18:17 +01:00 |
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MerryMage
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b2de47954b
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EmitX64: Emit correct cycle count on cond failure
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2016-08-18 18:16:18 +01:00 |
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Lioncash
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841098a0bc
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ir: separate components out a little more
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2016-08-17 20:46:21 +01:00 |
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MerryMage
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7d7ac0af71
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Optimization: Make SVC use RSB
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2016-08-15 15:02:08 +01:00 |
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MerryMage
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6c45619aa1
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Optimization: Implement terminal LinkBlockFast
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2016-08-15 14:33:17 +01:00 |
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MerryMage
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960d14d18e
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Optimization: Implement Return Stack Buffer
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2016-08-13 00:10:23 +01:00 |
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MerryMage
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1029fd27ce
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Update documentation (2016-08-12)
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2016-08-12 18:17:31 +01:00 |
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MerryMage
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abd113f160
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EmitX64: Renamed patch_jmp_locations to patch_jg_locations
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2016-08-08 15:56:07 +01:00 |
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MerryMage
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a32063fa60
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EmitX64: Implement block linking
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2016-08-07 22:11:39 +01:00 |
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MerryMage
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aba705f6b9
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BackendX64: Merge Routines into BlockOfCode
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2016-08-07 18:08:48 +01:00 |
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Tillmann Karras
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af27ef8d6c
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Optionally disassemble x86_64 code using LLVM
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2016-08-05 02:08:41 +01:00 |
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Tillmann Karras
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306e070ab5
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Use opcodes.inc for emit_x64.h
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2016-08-03 00:44:08 +01:00 |
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MerryMage
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be87038ffd
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IROpt: Port get/set elimination pass to current IR
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2016-08-02 11:51:05 +01:00 |
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MerryMage
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51448aa06d
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More Speed
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2016-07-22 23:55:00 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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Subv
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703a46ec99
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Pass the current IR::Block by reference to the emitter.
This avoids calling the copy constructor more times than needed.
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2016-07-18 11:27:33 -05:00 |
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MerryMage
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3720da4e19
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Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
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2016-07-16 19:23:42 +01:00 |
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MerryMage
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9b2aff166a
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Implement arm_SVC
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2016-07-14 14:29:46 +01:00 |
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MerryMage
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7d7751c157
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Allow IR blocks to require a cond for block entry.
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
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2016-07-14 12:52:53 +01:00 |
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MerryMage
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09420d190b
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IR: Implement IR microinstructions ALUWritePC and LoadWritePC
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2016-07-12 10:58:14 +01:00 |
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MerryMage
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1410221b47
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Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
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2016-07-11 23:11:05 +01:00 |
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MerryMage
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e7922e4fef
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Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
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2016-07-11 22:43:53 +01:00 |
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MerryMage
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d11df9067d
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Implement thumb1_BIC_reg
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2016-07-10 10:44:45 +08:00 |
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MerryMage
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98a64a92b1
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Implement thumb1_ORR_reg
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2016-07-10 09:06:38 +08:00 |
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MerryMage
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8145b33882
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Implemented thumb1_ROR_reg
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2016-07-10 08:18:17 +08:00 |
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MerryMage
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92142d5a22
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Implement thumb1_SUB_reg
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2016-07-08 18:49:30 +08:00 |
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MerryMage
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df0c324923
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Implement thumb1_EOR_reg
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2016-07-08 18:14:54 +08:00 |
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MerryMage
|
8a0511d297
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Implement thumb1_AND_reg
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2016-07-08 17:44:53 +08:00 |
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MerryMage
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d0b48bfb59
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Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
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2016-07-08 17:44:51 +08:00 |
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MerryMage
|
f31b530703
|
Fuzz thumb instructions
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2016-07-07 19:01:47 +08:00 |
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MerryMage
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5711e62419
|
Implement terminal instructions
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2016-07-07 17:53:09 +08:00 |
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MerryMage
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14388ea690
|
Proper implementation of Arm::Translate
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2016-07-04 21:37:50 +08:00 |
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MerryMage
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d743adf518
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Reorganisation, Import Skyeye, This is a mess
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2016-07-04 17:22:11 +08:00 |
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MerryMage
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65df15633d
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First Commit
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2016-07-01 21:01:06 +08:00 |
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