MerryMage
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88ae7fce52
|
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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d497464c9f
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a64_jitstate: Have 128-bit wide spills
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
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b513b2ef05
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IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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16fa2cd8f6
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a64_emit_x64: Use xword from Xbyak::util
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2020-04-22 20:44:38 +01:00 |
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Lioncash
|
67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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7abd673a49
|
A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
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2020-04-22 20:44:38 +01:00 |
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Lioncash
|
d3b1a72bca
|
unicorn: Display EC and ISS separately beside the full ESR value
Makes it a little nicer to pick out the exception class details at a glance
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2020-04-22 20:44:38 +01:00 |
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Lioncash
|
8fa9849c25
|
unicorn: Use static_cast instead of reinterpret_cast
It's well-defined to cast from void* back to the original pointer type.
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
ba3d6da0c8
|
load_store_register_unprivileged: bug: LDTRSW
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
75756137c6
|
A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
d5283e46e8
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
4ce9c65cfb
|
reg_alloc: Use std::exchange
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2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
|
e0c12ec2ad
|
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
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Lioncash
|
cf824fb2b2
|
unicorn_load: Minor Windows-related changes
- Add missing include
- Fix a potential compilation issue where the constructor wouldn't be able to execute, as it would be private.
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
a8ed248a13
|
tests/A64: Test memory writes
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
94383fd934
|
microinstruction: Missed A64{Read,Write}Memory128 from opcode information
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
d124a1d761
|
emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable
For CPUs that didn't support SSE4.1, this was a bug.
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2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
f1057aa362
|
tests: Fix truncation in GetFpcr()
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
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589ad7232f
|
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
ae880d8391
|
A64: Fix bugs and address review comments
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
3aeb7ca50c
|
Add missing returns
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
41e6e659c5
|
A64: Implement Load/Store register (unprivileged)
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2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
01a26fa644
|
fixup: travis: Test with disabled CPU feature detection
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2020-04-22 20:44:37 +01:00 |
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Lioncash
|
5281d3c6d5
|
CMakeLists: Add opcodes.inc to the source file list
Allows the file to show up nicely within IDEs
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
30936f5e94
|
travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
285fd22c30
|
IR: Add IR instruction VectorZeroUpper
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
da3e9a5704
|
a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
|
2020-04-22 20:44:37 +01:00 |
|
FernandoS27
|
ab84524806
|
Implemented SDIV and UDIV instructions
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2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
6033b05ca6
|
A64: Implement LDR/STR (immediate, SIMD&FP)
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2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
f698848e26
|
IR: Add IR instructions A64Memory{Read,Write}128
Add the Windows ABI implementation
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2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
e1df7ae621
|
IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
e00a522cba
|
IR: Add IR instruction VectorGetElement{8,16,32,64}
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
28ccd85e5c
|
IR: Add IR instruction ZeroExtendToQuad
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
af848c627d
|
block_of_code: Add ABI_RETURN2
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
1749780929
|
interface: Move Vector typedef to config.h
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
33bba6028c
|
bit_util: bug: Infinite loop in HighestSetBit
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
3caf192f60
|
A64: Implement DUP (general)
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2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
793753bf63
|
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
|
2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
8ee854232c
|
General: Default constructors and destructors where applicable
|
2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
d1e4526e1c
|
ir_emitter: Remove unused includes
|
2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
6f9216d544
|
A64: Implement RBIT
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
9b0a21915f
|
ir_emitted: Remove unimplemented IR instruction Unimplemented
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
db30e02ac8
|
emit_x64: Extract BlockRangeInformation, remove template parameter
|
2020-04-22 20:44:36 +01:00 |
|
MerryMage
|
58c4a25527
|
emit_x64: Use JitStateInfo
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
d4b05b28cf
|
A64: Implement CLS
This is not the cleanest implementation.
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
b8e26bfdc3
|
A64: Implement ADDP (vector)
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
eaf545877a
|
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
a554e4a329
|
backend_x64: Split emit_x64
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
2a493f8b50
|
fuzz_with_unicorn: Compare vectors
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
394bd57bb6
|
microinstruction: bug: Add missing opcodes
|
2020-04-22 20:42:46 +01:00 |
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