The guest program often accesses the NZCV flags directly much less
often than we need to use them for jumps and other such uses.
Therefore, we store our flags in cpsr_nzcv in a x64-friendly format.
This allows for a reduction in conditional jump related code.
Several issues:
1. Several terminal instructions did not stop at the end of a single-step block
2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag
We also introduce the enable_optimizations parameter to the A32 frontend.
Instead of looking up the page table like:
table[addr >> 12][addr & 0xFFF]
We can use a global offset on the table to query the memory like:
table[addr >> 12][addr]
This saves two instructions on *every* memory access within the recompiler.
Original change by degasus in A64 emitter
Also solves a performance regression initially introduced by b6e8297e369f2dc4758bafe944e51efb8d1a2552,
primarily due to excessively mismatched load/store sizes causing less than optimal load-to-store forwarding.
Removes unnecessary header dependencies that have accumulated over time
as changes have been made. Lessens the amount of files that need to be
rebuilt when the headers change.
Removes a boost header from the public includes in favor of using the
standard-provided std::variant.
The use of boost in public interfaces is often a dealbreaker for some
people. Given we use std::optional in the header already, we can
transition over to std::variant from boost::variant.
With this removal, this makes all of our dependencies internal to the
library itself.
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
The AddressRange structure isn't used anywhere within the codebase, so
this can be removed. Particularly because there's no real appeal/heavy
potential use of it in the future that isn't trivial to add back if
needed.
* The MSB for each byte in cpsr_ge were not being appropriately set.
* We also expand test coverage to test this case.
* We fix the disassembly of the MSR (imm) and MSR (reg) instructions as well.
