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364 commits

Author SHA1 Message Date
MerryMage
52268298a8 a64_emit_x64: Perform RSB predictions 2020-04-22 20:46:12 +01:00
MerryMage
98ec9c5f90 A32: Change UserCallbacks to be similar to A64's interface 2020-04-22 20:46:12 +01:00
Lioncash
b9ce660113 reg_alloc: std::move RegAlloc's function argument 2020-04-22 20:46:12 +01:00
Lioncash
ed561d6653 General: Add missing override specifiers 2020-04-22 20:46:12 +01:00
MerryMage
b2d99eddc6 EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128 2020-04-22 20:46:12 +01:00
MerryMage
54de64f5bf a64_emit_x64: bug: x64 sign-extends 32-bit immediates 2020-04-22 20:46:12 +01:00
MerryMage
6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass 2020-04-22 20:46:12 +01:00
MerryMage
af793c2527 {a32,a64}_interface: Predict entrypoint 2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050 A64: Implement EXTR 2020-04-22 20:46:12 +01:00
MerryMage
d497464c9f a64_jitstate: Have 128-bit wide spills 2020-04-22 20:44:38 +01:00
MerryMage
b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
MerryMage
16fa2cd8f6 a64_emit_x64: Use xword from Xbyak::util 2020-04-22 20:44:38 +01:00
Lioncash
67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2020-04-22 20:44:38 +01:00
MerryMage
4ce9c65cfb reg_alloc: Use std::exchange 2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2020-04-22 20:44:38 +01:00
MerryMage
d124a1d761 emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable 
For CPUs that didn't support SSE4.1, this was a bug.
 2020-04-22 20:44:38 +01:00
MerryMage
01a26fa644 fixup: travis: Test with disabled CPU feature detection 2020-04-22 20:44:37 +01:00
MerryMage
30936f5e94 travis: Test with disabled CPU feature detection 
Ensure that fallbacks are working correctly.
 2020-04-22 20:44:37 +01:00
MerryMage
285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
MerryMage
da3e9a5704 a64_emit_x64: bug: EmitA64WriteMemory128 should write not read 2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806 Implemented SDIV and UDIV instructions 2020-04-22 20:44:37 +01:00
MerryMage
f698848e26 IR: Add IR instructions A64Memory{Read,Write}128 
Add the Windows ABI implementation
 2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage
e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage
28ccd85e5c IR: Add IR instruction ZeroExtendToQuad 2020-04-22 20:44:37 +01:00
MerryMage
af848c627d block_of_code: Add ABI_RETURN2 2020-04-22 20:44:37 +01:00
MerryMage
1749780929 interface: Move Vector typedef to config.h 2020-04-22 20:44:37 +01:00
MerryMage
793753bf63 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2020-04-22 20:44:37 +01:00
Lioncash
8ee854232c General: Default constructors and destructors where applicable 2020-04-22 20:44:37 +01:00
MerryMage
db30e02ac8 emit_x64: Extract BlockRangeInformation, remove template parameter 2020-04-22 20:44:36 +01:00
MerryMage
58c4a25527 emit_x64: Use JitStateInfo 2020-04-22 20:42:46 +01:00
MerryMage
eaf545877a IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2020-04-22 20:42:46 +01:00
MerryMage
a554e4a329 backend_x64: Split emit_x64 2020-04-22 20:42:46 +01:00
Lioncash
b612782445 opcodes: Add 64-bit CountLeadingZeroes opcode 2020-04-22 20:42:46 +01:00
Lioncash
b08be71775 a32/a64_emit_x64: Remove unused includes 2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536 A64: Implement AND (vector) 2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2020-04-22 20:42:46 +01:00
MerryMage
9a812b0c61 reg_alloc: GetBitWidth: Add UNREACHABLE 2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage
6395f09f94 IR: Implement Conditional Select 2020-04-22 20:42:45 +01:00
MerryMage
19da68568e A64/translate/branch: bug: Read-after-write error in BLR 2020-04-22 20:42:45 +01:00
MerryMage
cdbc8d07a5 A64: Implement MOVN, MOVZ, MOVK 2020-04-22 20:42:45 +01:00
MerryMage
c6a091d874 A64: Optimization: Merge interpret blocks 2020-04-22 20:42:45 +01:00
MerryMage
996ffd5488 a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 2020-04-22 20:42:45 +01:00
MerryMage
e4615a4562 emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 2020-04-22 20:42:45 +01:00
MerryMage
0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b Misc. fixups of MSVC build 2020-04-22 20:42:45 +01:00
MerryMage
72a793f5b0 ir_opt: Split off A32 specific passes 2020-04-22 20:42:45 +01:00